#define MAX_PWM_FREQ SR_MHZ(20)
#define PWM_CLOCK SR_MHZ(200)
+/* usb vendor class control requests to the cypress FX2 microcontroller */
+#define CMD_EEPROM 0xa2 /* ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_INIT 0x50 /* used before and after FPGA bitstream loading */
+#define CMD_FPGA_SPI 0x20 /* access registers in the FPGA over SPI bus, ctrl_in reads, ctrl_out writes */
+#define CMD_FPGA_ENABLE 0x10
+#define CMD_BULK_RESET 0x38 /* flush FX2 usb endpoint 6 IN fifos */
+#define CMD_BULK_START 0x30 /* begin transfer of capture data via usb endpoint 6 IN */
+#define CMD_KAUTH 0x60 /* communicate with authentication ic U10, not used */
+
/* registers for control request 32: */
#define CTRL_RUN 0x00
#define CTRL_PWM_EN 0x02
struct drv_context *drvc;
struct sr_usb_dev_inst *usb;
struct sr_resource bitstream;
- uint32_t cmd;
+ uint8_t buffer[sizeof(uint32_t)];
+ uint8_t *wrptr;
uint8_t cmd_resp;
uint8_t block[4096];
int len, act_len;
}
devc->bitstream_size = (uint32_t)bitstream.size;
- WL32(&cmd, devc->bitstream_size);
- if ((ret = ctrl_out(sdi, 80, 0x00, 0, &cmd, sizeof(cmd))) != SR_OK) {
+ wrptr = buffer;
+ write_u32le_inc(&wrptr, devc->bitstream_size);
+ if ((ret = ctrl_out(sdi, CMD_FPGA_INIT, 0x00, 0, buffer, wrptr - buffer)) != SR_OK) {
sr_err("failed to give upload init command");
sr_resource_close(drvc->sr_ctx, &bitstream);
return ret;
return ret;
sr_info("FPGA bitstream upload (%" PRIu64 " bytes) done.", bitstream.size);
- if ((ret = ctrl_in(sdi, 80, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_FPGA_INIT, 0x00, 0, &cmd_resp, sizeof(cmd_resp))) != SR_OK) {
sr_err("failed to read response after FPGA bitstream upload");
return ret;
}
g_usleep(30000);
- if ((ret = ctrl_out(sdi, 16, 0x01, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x01, 0, NULL, 0)) != SR_OK) {
sr_err("failed enable fpga");
return ret;
}
{
struct dev_context *devc;
float o1, o2, v1, v2, f;
- uint32_t cfg;
+ uint32_t cfgval;
+ uint8_t buffer[sizeof(uint32_t)];
+ uint8_t *wrptr;
int ret;
devc = sdi->priv;
o1 = 15859969; v1 = 0.45;
o2 = 15860333; v2 = 1.65;
f = (o2 - o1) / (v2 - v1);
- WL32(&cfg, (uint32_t)(o1 + (voltage - v1) * f));
+ cfgval = (uint32_t)(o1 + (voltage - v1) * f);
+ sr_dbg("set threshold voltage %.2fV, raw value 0x%lx",
+ voltage, (unsigned long)cfgval);
- sr_dbg("set threshold voltage %.2fV", voltage);
- ret = ctrl_out(sdi, 32, CTRL_THRESHOLD, 0, &cfg, sizeof(cfg));
+ wrptr = buffer;
+ write_u32le_inc(&wrptr, cfgval);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_THRESHOLD, 0, buffer, wrptr - buffer);
if (ret != SR_OK) {
- sr_err("error setting new threshold voltage of %.2fV (%d)", voltage, RL16(&cfg));
+ sr_err("Error setting %.2fV threshold voltage (%d)",
+ voltage, ret);
return ret;
}
devc->threshold_voltage = voltage;
if (p2) cfg |= 1 << 1;
sr_dbg("set pwm enable %d %d", p1, p2);
- ret = ctrl_out(sdi, 32, CTRL_PWM_EN, 0, &cfg, sizeof(cfg));
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM_EN, 0, &cfg, sizeof(cfg));
if (ret != SR_OK) {
sr_err("error setting new pwm enable 0x%02x", cfg);
return ret;
pwm_setting_dev_t cfg;
pwm_setting_t *setting;
int ret;
+ uint8_t buf[2 * sizeof(uint32_t)];
+ uint8_t *wrptr;
devc = sdi->priv;
cfg.duty = (uint32_t)(0.5f + (cfg.period * duty / 100.));
sr_dbg("set pwm%d period %d, duty %d", which, cfg.period, cfg.duty);
- pwm_setting_dev_le(cfg);
- ret = ctrl_out(sdi, 32, CTRL_PWM[which - 1], 0, &cfg, sizeof(cfg));
+ wrptr = buf;
+ write_u32le_inc(&wrptr, cfg.period);
+ write_u32le_inc(&wrptr, cfg.duty);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_PWM[which - 1], 0, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting new pwm%d config %d %d", which, cfg.period, cfg.duty);
return ret;
setting = &devc->pwm_setting[which - 1];
setting->freq = freq;
setting->duty = duty;
- setting->dev = cfg;
return SR_OK;
}
struct sr_trigger_match *match;
uint16_t ch_mask;
int ret;
+ uint8_t buf[4 * sizeof(uint32_t)];
+ uint8_t *wrptr;
devc = sdi->priv;
trigger = sr_session_trigger_get(sdi->session);
devc->had_triggers_configured = cfg.enabled != 0;
- trigger_cfg_le(cfg);
- ret = ctrl_out(sdi, 32, CTRL_TRIGGER, 16, &cfg, sizeof(cfg));
+ wrptr = buf;
+ write_u32le_inc(&wrptr, cfg.channels);
+ write_u32le_inc(&wrptr, cfg.enabled);
+ write_u32le_inc(&wrptr, cfg.level);
+ write_u32le_inc(&wrptr, cfg.high_or_falling);
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_TRIGGER, 16, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting trigger config!");
return ret;
static int set_sample_config(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
- sample_config_t cfg;
double clock_divisor;
uint64_t psa;
uint64_t total;
int ret;
+ uint16_t divisor;
+ uint8_t buf[2 * sizeof(uint32_t) + 48 / 8 + sizeof(uint16_t)];
+ uint8_t *wrptr;
devc = sdi->priv;
total = 128 * 1024 * 1024;
clock_divisor = MAX_SAMPLE_RATE / (double)devc->cur_samplerate;
if (clock_divisor > 0xffff)
clock_divisor = 0xffff;
- cfg.clock_divisor = (uint16_t)(clock_divisor + 0.5);
- devc->cur_samplerate = MAX_SAMPLE_RATE / cfg.clock_divisor;
+ divisor = (uint16_t)(clock_divisor + 0.5);
+ devc->cur_samplerate = MAX_SAMPLE_RATE / divisor;
if (devc->limit_samples > MAX_SAMPLE_DEPTH) {
sr_err("too high sample depth: %" PRIu64, devc->limit_samples);
return SR_ERR;
}
- cfg.sample_depth = devc->limit_samples;
devc->pre_trigger_size = (devc->capture_ratio * devc->limit_samples) / 100;
- psa = devc->pre_trigger_size * 256;
- cfg.psa = (uint32_t)(psa & 0xffffffff);
- cfg.u1 = (uint16_t)((psa >> 32) & 0xffff);
- cfg.u2 = (uint32_t)((total * devc->capture_ratio) / 100);
-
sr_dbg("set sampling configuration %.0fkHz, %d samples, trigger-pos %d%%",
- devc->cur_samplerate/1e3, (unsigned int)cfg.sample_depth, (unsigned int)devc->capture_ratio);
+ devc->cur_samplerate / 1e3, (unsigned int)devc->limit_samples, (unsigned int)devc->capture_ratio);
- sample_config_le(cfg);
- ret = ctrl_out(sdi, 32, CTRL_SAMPLING, 0, &cfg, sizeof(cfg));
+ psa = devc->pre_trigger_size * 256;
+ wrptr = buf;
+ write_u32le_inc(&wrptr, devc->limit_samples);
+ write_u48le_inc(&wrptr, psa);
+ write_u32le_inc(&wrptr, (total * devc->capture_ratio) / 100);
+ write_u16le_inc(&wrptr, clock_divisor);
+
+ ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_SAMPLING, 0, buf, wrptr - buf);
if (ret != SR_OK) {
sr_err("error setting sample config!");
return ret;
uint16_t state;
int ret;
- if ((ret = ctrl_in(sdi, 32, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, CTRL_RUN, 0, &state, sizeof(state))) != SR_OK) {
sr_err("failed to read run state!");
return ret;
}
{
int ret;
- if ((ret = ctrl_out(sdi, 32, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_RUN, 0, &fast_blinking, sizeof(fast_blinking))) != SR_OK) {
sr_err("failed to send set-run-mode command %d", fast_blinking);
return ret;
}
{
struct dev_context *devc;
int ret;
+ uint8_t buf[3 * sizeof(uint32_t)];
+ const uint8_t *rdptr;
devc = sdi->priv;
- if ((ret = ctrl_in(sdi, 32, CTRL_BULK, 0, &devc->info, sizeof(devc->info))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_FPGA_SPI, CTRL_BULK, 0, buf, sizeof(buf))) != SR_OK) {
sr_err("failed to read capture info!");
return ret;
}
- capture_info_host(devc->info);
+
+ rdptr = buf;
+ devc->info.n_rep_packets = read_u32le_inc(&rdptr);
+ devc->info.n_rep_packets_before_trigger = read_u32le_inc(&rdptr);
+ devc->info.write_pos = read_u32le_inc(&rdptr);
sr_dbg("capture info: n_rep_packets: 0x%08x/%d, before_trigger: 0x%08x/%d, write_pos: 0x%08x%d",
devc->info.n_rep_packets, devc->info.n_rep_packets,
{
char fw_file[1024];
snprintf(fw_file, sizeof(fw_file) - 1, UC_FIRMWARE, product_id);
- return ezusb_upload_firmware(sr_ctx, dev, 0, fw_file);
+ return ezusb_upload_firmware(sr_ctx, dev, USB_CONFIGURATION, fw_file);
}
SR_PRIV int la2016_setup_acquisition(const struct sr_dev_inst *sdi)
return ret;
cmd = 0;
- if ((ret = ctrl_out(sdi, 32, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, 0x03, 0, &cmd, sizeof(cmd))) != SR_OK) {
sr_err("failed to send stop sampling command");
return ret;
}
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
int ret;
- uint32_t bulk_cfg[2];
+ uint8_t wrbuf[2 * sizeof(uint32_t)];
+ uint8_t *wrptr;
uint32_t to_read;
uint8_t *buffer;
if ((ret = get_capture_info(sdi)) != SR_OK)
return ret;
- devc->n_transfer_packets_to_read = devc->info.n_rep_packets / 5;
- devc->n_bytes_to_read = devc->n_transfer_packets_to_read * sizeof(transfer_packet_t);
+ devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
+ devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
sr_dbg("want to read %d tfer-packets starting from pos %d",
devc->n_transfer_packets_to_read, devc->read_pos);
- if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to reset bulk state");
return ret;
}
- WL32(&bulk_cfg[0], devc->read_pos);
- WL32(&bulk_cfg[1], devc->n_bytes_to_read);
sr_dbg("will read from 0x%08x, 0x%08x bytes", devc->read_pos, devc->n_bytes_to_read);
- if ((ret = ctrl_out(sdi, 32, CTRL_BULK, 0, &bulk_cfg, sizeof(bulk_cfg))) != SR_OK) {
+ wrptr = wrbuf;
+ write_u32le_inc(&wrptr, devc->read_pos);
+ write_u32le_inc(&wrptr, devc->n_bytes_to_read);
+ if ((ret = ctrl_out(sdi, CMD_FPGA_SPI, CTRL_BULK, 0, wrbuf, wrptr - wrbuf)) != SR_OK) {
sr_err("failed to send bulk config");
return ret;
}
- if ((ret = ctrl_out(sdi, 48, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_BULK_START, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to unblock bulk transfers");
return ret;
}
devc = sdi->priv;
- if ((ret = ctrl_in(sdi, 162, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x20, 0, &i1, sizeof(i1))) != SR_OK) {
sr_err("failed to read i1");
return ret;
}
sr_dbg("i1: 0x%08x", i1);
- if ((ret = ctrl_in(sdi, 162, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_EEPROM, 0x08, 0, &i2, sizeof(i2))) != SR_OK) {
sr_err("failed to read i2");
return ret;
}
unknown_cmd1 = unknown_cmd1_342;
expected_unknown_resp1 = expected_unknown_resp1_342;
}
- if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd1, sizeof(unknown_cmd1_340))) != SR_OK) {
sr_err("failed to send unknown_cmd1");
return ret;
}
g_usleep(80 * 1000);
- if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp1, sizeof(unknown_resp1))) != SR_OK) {
sr_err("failed to read unknown_resp1");
return ret;
}
if (state != 0x85e9)
sr_warn("expect run state to be 0x85e9, but it reads 0x%04x", state);
- if ((ret = ctrl_out(sdi, 96, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_KAUTH, 0x00, 0, unknown_cmd2, sizeof(unknown_cmd2))) != SR_OK) {
sr_err("failed to send unknown_cmd2");
return ret;
}
g_usleep(80 * 1000);
- if ((ret = ctrl_in(sdi, 96, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
+ if ((ret = ctrl_in(sdi, CMD_KAUTH, 0x00, 0, unknown_resp2, sizeof(unknown_resp2))) != SR_OK) {
sr_err("failed to read unknown_resp2");
return ret;
}
if (memcmp(unknown_resp2, expected_unknown_resp2, sizeof(unknown_resp2)))
sr_dbg("unknown_cmd2 response is not as expected!");
- if ((ret = ctrl_out(sdi, 56, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_BULK_RESET, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to send unknown_cmd3");
return ret;
}
{
int ret;
- if ((ret = ctrl_out(sdi, 16, 0x00, 0, NULL, 0)) != SR_OK) {
+ if ((ret = ctrl_out(sdi, CMD_FPGA_ENABLE, 0x00, 0, NULL, 0)) != SR_OK) {
sr_err("failed to send deinit command");
return ret;
}
projects / libsigrok.git / blobdiff