#define REG_PWM1 0x70 /* Write config for user PWM1. */
#define REG_PWM2 0x78 /* Write config for user PWM2. */
+/* Bit patterns to write to REG_CAPT_MODE. */
+#define CAPTMODE_TO_RAM 0x00
+#define CAPTMODE_STREAM 0x01
+
/* Bit patterns to write to REG_RUN, setup run mode. */
#define RUNMODE_HALT 0x00
#define RUNMODE_RUN 0x03
#define RUNSTATE_TRGD_BIT (1UL << 2)
#define RUNSTATE_POST_BIT (1UL << 3)
-/*
- * Properties related to the layout of capture data downloads.
- *
- * TODO Check the layout of 32 channel models' capture data. Could it be
- * 3x (u32 + u8) instead of 5x (u16 + u8) perhaps? Same 16 bytes chunk
- * but fewer packets per chunk and thus per transfer? Which questions
- * the NUM_PACKETS_IN_CHUNK literal, maybe needs to be a runtime value?
- */
-#define NUM_PACKETS_IN_CHUNK 5
-#define TRANSFER_PACKET_LENGTH 16
-
static int ctrl_in(const struct sr_dev_inst *sdi,
uint8_t bRequest, uint16_t wValue, uint16_t wIndex,
void *data, uint16_t wLength)
struct dev_context *devc;
struct sr_trigger *trigger;
struct trigger_cfg {
- uint32_t channels;
- uint32_t enabled;
+ uint32_t channels; /* Actually: Enabled channels? */
+ uint32_t enabled; /* Actually: Triggering channels? */
uint32_t level;
uint32_t high_or_falling;
} cfg;
}
}
sr_dbg("Set trigger config: "
- "channels 0x%04x, trigger-enabled 0x%04x, "
+ "enabled-channels 0x%04x, triggering-channels 0x%04x, "
"level-triggered 0x%04x, high/falling 0x%04x.",
cfg.channels, cfg.enabled, cfg.level, cfg.high_or_falling);
devc->info.n_rep_packets_before_trigger,
devc->info.write_pos, devc->info.write_pos);
- if (devc->info.n_rep_packets % NUM_PACKETS_IN_CHUNK) {
- sr_warn("Unexpected packets count %lu, not a multiple of %d.",
+ if (devc->info.n_rep_packets % devc->packets_per_chunk) {
+ sr_warn("Unexpected packets count %lu, not a multiple of %lu.",
(unsigned long)devc->info.n_rep_packets,
- NUM_PACKETS_IN_CHUNK);
+ (unsigned long)devc->packets_per_chunk);
}
return SR_OK;
if (ret != SR_OK)
return ret;
- cmd = 0;
+ cmd = CAPTMODE_TO_RAM;
ret = ctrl_out(sdi, CMD_FPGA_SPI, REG_CAPT_MODE, 0, &cmd, sizeof(cmd));
if (ret != SR_OK) {
sr_err("Cannot send command to stop sampling.");
if (ret != SR_OK)
return ret;
- devc->n_transfer_packets_to_read = devc->info.n_rep_packets / NUM_PACKETS_IN_CHUNK;
- devc->n_bytes_to_read = devc->n_transfer_packets_to_read * TRANSFER_PACKET_LENGTH;
+ devc->n_transfer_packets_to_read = devc->info.n_rep_packets;
+ devc->n_transfer_packets_to_read /= devc->packets_per_chunk;
+ devc->n_bytes_to_read = devc->n_transfer_packets_to_read;
+ devc->n_bytes_to_read *= TRANSFER_PACKET_LENGTH;
devc->read_pos = devc->info.write_pos - devc->n_bytes_to_read;
devc->n_reps_until_trigger = devc->info.n_rep_packets_before_trigger;
sample_value = 0;
rp = packets;
while (num_xfers--) {
- /* XXX model dependent? 5 or 3? */
- num_pkts = NUM_PACKETS_IN_CHUNK;
+ num_pkts = devc->packets_per_chunk;
while (num_pkts--) {
/* TODO Verify 32channel layout. */
/* Initiate the download of acquired sample data. */
std_session_send_df_frame_begin(sdi);
+ devc->frame_begin_sent = TRUE;
ret = la2016_start_download(sdi, receive_transfer);
if (ret != SR_OK) {
sr_err("Cannot start acquisition data download.");
feed_queue_logic_flush(devc->feed_queue);
feed_queue_logic_free(devc->feed_queue);
devc->feed_queue = NULL;
- std_session_send_df_frame_end(sdi);
+ if (devc->frame_begin_sent) {
+ std_session_send_df_frame_end(sdi);
+ devc->frame_begin_sent = FALSE;
+ }
std_session_send_df_end(sdi);
sr_dbg("Download finished, done post processing.");