]> sigrok.org Git - libsigrok.git/blobdiff - src/hardware/fx2lafw/dslogic.h
fx2lafw/dslogic: Various cosmetics and whitespace fixes.
[libsigrok.git] / src / hardware / fx2lafw / dslogic.h
index e6646513c6a40c0db1d1f555227596fbad7ab737..f74367ade59499de7d2811b2f2767a5aec7c6c57 100644 (file)
@@ -27,6 +27,7 @@
 #define DS_CMD_START                   0xb2
 #define DS_CMD_FPGA_FW                 0xb3
 #define DS_CMD_CONFIG                  0xb4
+#define DS_CMD_VTH                     0xb8
 
 #define DS_NUM_TRIGGER_STAGES          16
 #define DS_START_FLAGS_STOP            (1 << 7)
@@ -34,6 +35,9 @@
 #define DS_START_FLAGS_SAMPLE_WIDE     (1 << 5)
 #define DS_START_FLAGS_MODE_LA         (1 << 4)
 
+#define DS_MAX_LOGIC_DEPTH             SR_MHZ(16)
+#define DS_MAX_LOGIC_SAMPLERATE                SR_MHZ(100)
+
 enum dslogic_operation_modes {
        DS_OP_NORMAL,
        DS_OP_INTERNAL_TEST,
@@ -41,6 +45,16 @@ enum dslogic_operation_modes {
        DS_OP_LOOPBACK_TEST,
 };
 
+enum {
+       DS_VOLTAGE_RANGE_18_33_V,       /* 1.8V and 3.3V logic */
+       DS_VOLTAGE_RANGE_5_V,           /* 5V logic */
+};
+
+enum {
+       DS_EDGE_RISING,
+       DS_EDGE_FALLING,
+};
+
 struct dslogic_version {
        uint8_t major;
        uint8_t minor;
@@ -130,5 +144,7 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
 SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
+SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
+SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
 
 #endif