fx2lafw/dslogic: Imported FPGA config mode flags

[libsigrok.git] / src / hardware / fx2lafw / dslogic.h

diff --git a/src/hardware/fx2lafw/dslogic.h b/src/hardware/fx2lafw/dslogic.h
index 6cb827d3e211bf79d830fcae7aad86d252d86eae..50e0a63df3d74bb75ee565a3a59a3d611c712e24 100644 (file)
--- a/src/hardware/fx2lafw/dslogic.h
+++ b/src/hardware/fx2lafw/dslogic.h
@@ -25,9 +25,16 @@
 #define DS_CMD_GET_FW_VERSION          0xb0
 #define DS_CMD_GET_REVID_VERSION       0xb1
 #define DS_CMD_START                   0xb2
-#define DS_CMD_FPGA_FW                 0xb3
-#define DS_CMD_CONFIG                  0xb4
-#define DS_CMD_VTH                             0xb8
+#define DS_CMD_CONFIG                  0xb3
+#define DS_CMD_SETTING                 0xb4
+#define DS_CMD_CONTROL                 0xb5
+#define DS_CMD_STATUS                  0xb6
+#define DS_CMD_STATUS_INFO             0xb7
+#define DS_CMD_WR_REG                  0xb8
+#define DS_CMD_WR_NVM                  0xb9
+#define DS_CMD_RD_NVM                  0xba
+#define DS_CMD_RD_NVM_PRE              0xbb
+#define DS_CMD_GET_HW_INFO             0xbc
 
 #define DS_NUM_TRIGGER_STAGES          16
 #define DS_START_FLAGS_STOP            (1 << 7)
@@ -35,8 +42,28 @@
 #define DS_START_FLAGS_SAMPLE_WIDE     (1 << 5)
 #define DS_START_FLAGS_MODE_LA         (1 << 4)
 
-/* enable rle to capture more samples than this limit */
-#define DS_MAX_LOGIC_DEPTH     16000000
+#define DS_ADDR_COMB                   0x68
+#define DS_ADDR_EEWP                   0x70
+#define DS_ADDR_VTH                    0x78
+
+#define DS_MAX_LOGIC_DEPTH             SR_MHZ(16)
+#define DS_MAX_LOGIC_SAMPLERATE                SR_MHZ(100)
+
+#define DS_MODE_TRIG_EN                        (1 << 0)
+#define DS_MODE_CLK_TYPE               (1 << 1)
+#define DS_MODE_CLK_EDGE               (1 << 2)
+#define DS_MODE_RLE_MODE               (1 << 3)
+#define DS_MODE_DSO_MODE               (1 << 4)
+#define DS_MODE_HALF_MODE              (1 << 5)
+#define DS_MODE_QUAR_MODE              (1 << 6)
+#define DS_MODE_ANALOG_MODE            (1 << 7)
+#define DS_MODE_FILTER                 (1 << 8)
+#define DS_MODE_INSTANT                        (1 << 9)
+#define DS_MODE_STRIG_MODE             (1 << 11)
+#define DS_MODE_STREAM_MODE            (1 << 12)
+#define DS_MODE_LPB_TEST               (1 << 13)
+#define DS_MODE_EXT_TEST               (1 << 14)
+#define DS_MODE_INT_TEST               (1 << 15)
 
 enum dslogic_operation_modes {
        DS_OP_NORMAL,
@@ -45,14 +72,14 @@ enum dslogic_operation_modes {
        DS_OP_LOOPBACK_TEST,
 };
 
-enum  {
-           DS_VOLTAGE_RANGE_18_33_V,   /* 1.8V and 3.3V logic */
-           DS_VOLTAGE_RANGE_5_V,       /* 5V logic */
+enum {
+       DS_VOLTAGE_RANGE_18_33_V,       /* 1.8V and 3.3V logic */
+       DS_VOLTAGE_RANGE_5_V,           /* 5V logic */
 };
 
-enum{
+enum {
        DS_EDGE_RISING,
-       DS_EDGE_FALLING
+       DS_EDGE_FALLING,
 };
 
 struct dslogic_version {
@@ -145,5 +172,6 @@ SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi);
 SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth);
+SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc);
 
 #endif