dslogic: Add support for external clock edge selection.

[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index f912278fa23c7505462b50bb700dfd41b25eb70c..619544f94c8f02fb3a3d29d92089b05293e569ca 100644 (file)
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -36,6 +36,27 @@
 
 #define USB_TIMEOUT (3 * 1000)
 
+SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
+{
+       struct sr_usb_dev_inst *usb;
+       usb = sdi->conn;
+       int ret;
+       uint8_t cmd;
+
+       cmd = vth/5.0 * 255;
+       /* Send the control command. */
+       ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
+       LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
+               (unsigned char *)&cmd, sizeof(cmd), 3000);
+       if (ret < 0) {
+               sr_err("Unable to send VTH command: %s.",
+               libusb_error_name(ret));
+               return SR_ERR;
+       }
+
+       return SR_OK;
+}
+
 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
                const char *name)
 {
@@ -165,14 +186,13 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
        struct sr_trigger *trigger;
        struct sr_trigger_stage *stage;
        struct sr_trigger_match *match;
+
        struct dev_context *devc;
+       devc = sdi->priv;
        const GSList *l, *m;
        int channelbit, i = 0;
        uint16_t v16;
 
-       devc = sdi->priv;
-       devc->trigger_en = FALSE;
-
        cfg->trig_mask0[0] = 0xffff;
        cfg->trig_mask1[0] = 0xffff;
 
@@ -188,8 +208,33 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
        cfg->trig_count0[0] = 0;
        cfg->trig_count1[0] = 0;
 
-       if (!(trigger = sr_session_trigger_get(sdi->session)))
+       cfg->trig_pos = 0;
+       cfg->trig_sda = 0;
+       cfg->trig_glb = 0;
+       cfg->trig_adp = cfg->count - cfg->trig_pos - 1;
+
+       for (i = 1; i < 16; i++) {
+               cfg->trig_mask0[i] = 0xff;
+               cfg->trig_mask1[i] = 0xff;
+               cfg->trig_value0[i] = 0;
+               cfg->trig_value1[i] = 0;
+               cfg->trig_edge0[i] = 0;
+               cfg->trig_edge1[i] = 0;
+               cfg->trig_count0[i] = 0;
+               cfg->trig_count1[i] = 0;
+               cfg->trig_logic0[i] = 2;
+               cfg->trig_logic1[i] = 2;
+       }
+
+       cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
+       sr_dbg("pos: %d", cfg->trig_pos);
+
+       sr_dbg("configuring trigger");
+
+       if (!(trigger = sr_session_trigger_get(sdi->session))){
+               sr_dbg("No session trigger found");
                return SR_OK;
+       }
 
        for (l = trigger->stages; l; l = l->next) {
                stage = l->data;
@@ -199,7 +244,6 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
                                /* Ignore disabled channels with a trigger. */
                                continue;
                        channelbit = 1 << (match->channel->index);
-                       devc->trigger_en = TRUE; /* Triggered. */
                        /* Simple trigger support (event). */
                        if (match->match == SR_TRIGGER_ONE) {
                                cfg->trig_mask0[0] &= ~channelbit;
@@ -221,34 +265,19 @@ static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
                                cfg->trig_value1[0] |= channelbit;
                                cfg->trig_edge0[0] |= channelbit;
                                cfg->trig_edge1[0] |= channelbit;
-                       } else if (match->match == SR_TRIGGER_EDGE){
+                       } else if(match->match == SR_TRIGGER_EDGE){
                                cfg->trig_edge0[0] |= channelbit;
                                cfg->trig_edge1[0] |= channelbit;
                        }
                }
        }
-
-       if (devc->trigger_en) {
-               for (i = 1; i < 16; i++) {
-                       cfg->trig_mask0[i] = 0xff;
-                       cfg->trig_mask1[i] = 0xff;
-                       cfg->trig_value0[i] = 0;
-                       cfg->trig_value1[i] = 0;
-                       cfg->trig_edge0[i] = 0;
-                       cfg->trig_edge1[i] = 0;
-                       cfg->trig_count0[i] = 0;
-                       cfg->trig_count1[i] = 0;
-                       cfg->trig_logic0[i] = 2;
-                       cfg->trig_logic1[i] = 2;
-               }
-               v16 = RL16(&cfg->mode);
-               v16 |= 1 << 0;
-               WL16(&cfg->mode, v16);
-       }
-
+       v16 = RL16(&cfg->mode);
+       v16 |= 1 << 0;
+       WL16(&cfg->mode, v16);
        return SR_OK;
 }
 
+
 SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
 {
        struct dev_context *devc;
@@ -303,13 +332,15 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
         * 13   1 = loopback test mode
         * 12   1 = stream mode
         * 11   1 = serial trigger
-        * 8-12 unused
+        * 8-10 unused
         * 7    1 = analog mode
         * 6    1 = samplerate 400MHz
         * 5    1 = samplerate 200MHz or analog mode
         * 4    0 = logic, 1 = dso or analog
-        * 2-3  unused
-        * 1    0 = internal clock, 1 = external clock
+        * 3    unused
+        * 1-2  00 = internal clock, 
+        *              01 = external clock rising, 
+        *              11 = external clock falling
         * 0    1 = trigger enabled
         */
        v16 = 0x0000;
@@ -319,9 +350,15 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                v16 = 1 << 14;
        else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
                v16 = 1 << 13;
-       //if (devc->dslogic_external_clock)
-       //      v16 |= 1 << 1;
-       //v16 |= 1 << 0;
+       if (devc->dslogic_continuous_mode)
+               v16 |= 1 << 12;
+       if (devc->dslogic_external_clock){
+               v16 |= 1 << 1;
+               if (devc->dslogic_clock_edge == DS_EDGE_FALLING){
+                       v16 |= 1 << 2;
+               }
+       }
+
        WL16(&cfg.mode, v16);
        v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
        WL32(&cfg.divider, v32);