* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <unistd.h>
-#include <errno.h>
+#include <config.h>
#include <math.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
#include "dslogic.h"
-#define FW_BUFSIZE (4 * 1024)
+/*
+ * This should be larger than the FPGA bitstream image so that it'll get
+ * uploaded in one big operation. There seem to be issues when uploading
+ * it in chunks.
+ */
+#define FW_BUFSIZE (1024 * 1024)
#define FPGA_UPLOAD_DELAY (10 * 1000)
#define USB_TIMEOUT (3 * 1000)
-int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
- const char *filename)
+SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
+{
+ struct sr_usb_dev_inst *usb;
+ usb = sdi->conn;
+ int ret;
+ uint8_t cmd;
+
+ cmd = vth/5.0 * 255;
+ /* Send the control command. */
+ ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
+ LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
+ (unsigned char *)&cmd, sizeof(cmd), 3000);
+ if (ret < 0) {
+ sr_err("Unable to send VTH command: %s.",
+ libusb_error_name(ret));
+ return SR_ERR;
+ }
+
+ return SR_OK;
+}
+
+SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
+ const char *name)
{
- FILE *fw;
- struct stat st;
+ uint64_t sum;
+ struct sr_resource bitstream;
+ struct drv_context *drvc;
struct sr_usb_dev_inst *usb;
- int chunksize, result, ret;
unsigned char *buf;
- int sum, transferred;
+ ssize_t chunksize;
+ int transferred;
+ int result, ret;
uint8_t cmd[3];
- sr_dbg("Uploading FPGA firmware at %s.", filename);
-
+ drvc = sdi->driver->context;
usb = sdi->conn;
- if (stat(filename, &st) < 0) {
- sr_err("Unable to upload FPGA firmware: %s", g_strerror(errno));
- return SR_ERR;
- }
+
+ sr_dbg("Uploading FPGA firmware '%s'.", name);
+
+ result = sr_resource_open(drvc->sr_ctx, &bitstream,
+ SR_RESOURCE_FIRMWARE, name);
+ if (result != SR_OK)
+ return result;
/* Tell the device firmware is coming. */
memset(cmd, 0, sizeof(cmd));
LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
- return SR_ERR;
- }
- buf = g_malloc(FW_BUFSIZE);
-
- if (!(fw = g_fopen(filename, "rb"))) {
- sr_err("Unable to open %s for reading: %s.", filename, g_strerror(errno));
+ sr_resource_close(drvc->sr_ctx, &bitstream);
return SR_ERR;
}
/* Give the FX2 time to get ready for FPGA firmware upload. */
g_usleep(FPGA_UPLOAD_DELAY);
+ buf = g_malloc(FW_BUFSIZE);
sum = 0;
result = SR_OK;
while (1) {
- if ((chunksize = fread(buf, 1, FW_BUFSIZE, fw)) == 0)
+ chunksize = sr_resource_read(drvc->sr_ctx, &bitstream,
+ buf, FW_BUFSIZE);
+ if (chunksize < 0)
+ result = SR_ERR;
+ if (chunksize <= 0)
break;
if ((ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
break;
}
sum += transferred;
- sr_spew("Uploaded %d/%d bytes.", sum, st.st_size);
+ sr_spew("Uploaded %" PRIu64 "/%" PRIu64 " bytes.",
+ sum, bitstream.size);
if (transferred != chunksize) {
sr_err("Short transfer while uploading FPGA firmware.");
break;
}
}
- fclose(fw);
g_free(buf);
+ sr_resource_close(drvc->sr_ctx, &bitstream);
+
if (result == SR_OK)
sr_dbg("FPGA firmware upload done.");
return result;
}
-int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
+SR_PRIV int dslogic_start_acquisition(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
int ret;
devc = sdi->priv;
- mode.flags = 0;
+ mode.flags = DS_START_FLAGS_MODE_LA;
mode.sample_delay_h = mode.sample_delay_l = 0;
if (devc->sample_wide)
mode.flags |= DS_START_FLAGS_SAMPLE_WIDE;
return SR_OK;
}
-int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
+SR_PRIV int dslogic_stop_acquisition(const struct sr_dev_inst *sdi)
{
struct sr_usb_dev_inst *usb;
struct dslogic_mode mode;
return SR_OK;
}
-int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
+/*
+ * Get the session trigger and configure the FPGA structure
+ * accordingly.
+ */
+static int dslogic_set_trigger(const struct sr_dev_inst *sdi,
+ struct dslogic_fpga_config *cfg)
+{
+ struct sr_trigger *trigger;
+ struct sr_trigger_stage *stage;
+ struct sr_trigger_match *match;
+
+ struct dev_context *devc;
+ devc = sdi->priv;
+ const GSList *l, *m;
+ int channelbit, i = 0;
+ uint16_t v16;
+
+ cfg->trig_mask0[0] = 0xffff;
+ cfg->trig_mask1[0] = 0xffff;
+
+ cfg->trig_value0[0] = 0;
+ cfg->trig_value1[0] = 0;
+
+ cfg->trig_edge0[0] = 0;
+ cfg->trig_edge1[0] = 0;
+
+ cfg->trig_logic0[0] = 0;
+ cfg->trig_logic1[0] = 0;
+
+ cfg->trig_count0[0] = 0;
+ cfg->trig_count1[0] = 0;
+
+ cfg->trig_pos = 0;
+ cfg->trig_sda = 0;
+ cfg->trig_glb = 0;
+ cfg->trig_adp = cfg->count - cfg->trig_pos - 1;
+
+ for (i = 1; i < 16; i++) {
+ cfg->trig_mask0[i] = 0xff;
+ cfg->trig_mask1[i] = 0xff;
+ cfg->trig_value0[i] = 0;
+ cfg->trig_value1[i] = 0;
+ cfg->trig_edge0[i] = 0;
+ cfg->trig_edge1[i] = 0;
+ cfg->trig_count0[i] = 0;
+ cfg->trig_count1[i] = 0;
+ cfg->trig_logic0[i] = 2;
+ cfg->trig_logic1[i] = 2;
+ }
+
+ cfg->trig_pos = (uint32_t)(devc->capture_ratio / 100.0 * devc->limit_samples);
+ sr_dbg("pos: %d", cfg->trig_pos);
+
+ sr_dbg("configuring trigger");
+
+ if (!(trigger = sr_session_trigger_get(sdi->session))){
+ sr_dbg("No session trigger found");
+ return SR_OK;
+ }
+
+ for (l = trigger->stages; l; l = l->next) {
+ stage = l->data;
+ for (m = stage->matches; m; m = m->next) {
+ match = m->data;
+ if (!match->channel->enabled)
+ /* Ignore disabled channels with a trigger. */
+ continue;
+ channelbit = 1 << (match->channel->index);
+ /* Simple trigger support (event). */
+ if (match->match == SR_TRIGGER_ONE) {
+ cfg->trig_mask0[0] &= ~channelbit;
+ cfg->trig_mask1[0] &= ~channelbit;
+ cfg->trig_value0[0] |= channelbit;
+ cfg->trig_value1[0] |= channelbit;
+ } else if (match->match == SR_TRIGGER_ZERO) {
+ cfg->trig_mask0[0] &= ~channelbit;
+ cfg->trig_mask1[0] &= ~channelbit;
+ } else if (match->match == SR_TRIGGER_FALLING) {
+ cfg->trig_mask0[0] &= ~channelbit;
+ cfg->trig_mask1[0] &= ~channelbit;
+ cfg->trig_edge0[0] |= channelbit;
+ cfg->trig_edge1[0] |= channelbit;
+ } else if (match->match == SR_TRIGGER_RISING) {
+ cfg->trig_mask0[0] &= ~channelbit;
+ cfg->trig_mask1[0] &= ~channelbit;
+ cfg->trig_value0[0] |= channelbit;
+ cfg->trig_value1[0] |= channelbit;
+ cfg->trig_edge0[0] |= channelbit;
+ cfg->trig_edge1[0] |= channelbit;
+ } else if(match->match == SR_TRIGGER_EDGE){
+ cfg->trig_edge0[0] |= channelbit;
+ cfg->trig_edge1[0] |= channelbit;
+ }
+ }
+ }
+ v16 = RL16(&cfg->mode);
+ v16 |= 1 << 0;
+ WL16(&cfg->mode, v16);
+ return SR_OK;
+}
+
+
+SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
struct sr_usb_dev_inst *usb;
* 15 1 = internal test mode
* 14 1 = external test mode
* 13 1 = loopback test mode
- * 8-12 unused
+ * 12 1 = stream mode
+ * 11 1 = serial trigger
+ * 8-10 unused
* 7 1 = analog mode
* 6 1 = samplerate 400MHz
* 5 1 = samplerate 200MHz or analog mode
* 4 0 = logic, 1 = dso or analog
- * 2-3 unused
- * 1 0 = internal clock, 1 = external clock
+ * 3 unused
+ * 1-2 00 = internal clock,
+ * 01 = external clock rising,
+ * 11 = external clock falling
* 0 1 = trigger enabled
*/
v16 = 0x0000;
v16 = 1 << 14;
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
v16 = 1 << 13;
- if (devc->dslogic_external_clock)
- v16 |= 1 << 2;
- WL16(&cfg.mode, v16);
+ if (devc->dslogic_continuous_mode)
+ v16 |= 1 << 12;
+ if (devc->dslogic_external_clock){
+ v16 |= 1 << 1;
+ if (devc->dslogic_clock_edge == DS_EDGE_FALLING){
+ v16 |= 1 << 2;
+ }
+ }
+ WL16(&cfg.mode, v16);
v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
WL32(&cfg.divider, v32);
WL32(&cfg.count, devc->limit_samples);
+ dslogic_set_trigger(sdi, &cfg);
+
len = sizeof(struct dslogic_fpga_config);
ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
projects / libsigrok.git / blobdiff