dslogic: Add support for external clock edge selection.

[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index 0e4c5599bceb3590e1859d733a603b121419989f..619544f94c8f02fb3a3d29d92089b05293e569ca 100644 (file)
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -36,6 +36,27 @@
 
 #define USB_TIMEOUT (3 * 1000)
 
+SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
+{
+       struct sr_usb_dev_inst *usb;
+       usb = sdi->conn;
+       int ret;
+       uint8_t cmd;
+
+       cmd = vth/5.0 * 255;
+       /* Send the control command. */
+       ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
+       LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
+               (unsigned char *)&cmd, sizeof(cmd), 3000);
+       if (ret < 0) {
+               sr_err("Unable to send VTH command: %s.",
+               libusb_error_name(ret));
+               return SR_ERR;
+       }
+
+       return SR_OK;
+}
+
 SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
                const char *name)
 {
@@ -311,13 +332,15 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
         * 13   1 = loopback test mode
         * 12   1 = stream mode
         * 11   1 = serial trigger
-        * 8-12 unused
+        * 8-10 unused
         * 7    1 = analog mode
         * 6    1 = samplerate 400MHz
         * 5    1 = samplerate 200MHz or analog mode
         * 4    0 = logic, 1 = dso or analog
-        * 2-3  unused
-        * 1    0 = internal clock, 1 = external clock
+        * 3    unused
+        * 1-2  00 = internal clock, 
+        *              01 = external clock rising, 
+        *              11 = external clock falling
         * 0    1 = trigger enabled
         */
        v16 = 0x0000;
@@ -327,8 +350,15 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                v16 = 1 << 14;
        else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
                v16 = 1 << 13;
-       if (devc->dslogic_external_clock)
+       if (devc->dslogic_continuous_mode)
+               v16 |= 1 << 12;
+       if (devc->dslogic_external_clock){
                v16 |= 1 << 1;
+               if (devc->dslogic_clock_edge == DS_EDGE_FALLING){
+                       v16 |= 1 << 2;
+               }
+       }
+
        WL16(&cfg.mode, v16);
        v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
        WL32(&cfg.divider, v32);