fx2lafw/dslogic: Imported FPGA config mode flags

[libsigrok.git] / src / hardware / fx2lafw / dslogic.c

diff --git a/src/hardware/fx2lafw/dslogic.c b/src/hardware/fx2lafw/dslogic.c
index 9c74ff1af77539acec209d49a345963203f11aca..0e14caebdfe5b398122ed661050171faad7d8ddb 100644 (file)
--- a/src/hardware/fx2lafw/dslogic.c
+++ b/src/hardware/fx2lafw/dslogic.c
@@ -70,7 +70,7 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
        ssize_t chunksize;
        int transferred;
        int result, ret;
-       uint8_t cmd[3];
+       const uint8_t cmd[3] = {0, 0, 0};
 
        drvc = sdi->driver->context;
        usb = sdi->conn;
@@ -83,7 +83,6 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
                return result;
 
        /* Tell the device firmware is coming. */
-       memset(cmd, 0, sizeof(cmd));
        if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
                        LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
                        (unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
@@ -331,36 +330,19 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                return SR_ERR;
        }
 
-       /*
-        * 15   1 = internal test mode
-        * 14   1 = external test mode
-        * 13   1 = loopback test mode
-        * 12   1 = stream mode
-        * 11   1 = serial trigger
-        * 8-10 unused
-        * 7    1 = analog mode
-        * 6    1 = samplerate 400MHz
-        * 5    1 = samplerate 200MHz or analog mode
-        * 4    0 = logic, 1 = dso or analog
-        * 3    1 = RLE encoding (enable for more than 16 Megasamples)
-        * 1-2  00 = internal clock,
-        *      01 = external clock rising,
-        *      11 = external clock falling
-        * 0    1 = trigger enabled
-        */
        v16 = 0x0000;
        if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
-               v16 = 1 << 15;
+               v16 = DS_MODE_INT_TEST;
        else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
-               v16 = 1 << 14;
+               v16 = DS_MODE_EXT_TEST;
        else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
-               v16 = 1 << 13;
+               v16 = DS_MODE_LPB_TEST;
        if (devc->dslogic_continuous_mode)
-               v16 |= 1 << 12;
+               v16 |= DS_MODE_STREAM_MODE;
        if (devc->dslogic_external_clock) {
-               v16 |= 1 << 1;
+               v16 |= DS_MODE_CLK_TYPE;
                if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
-                       v16 |= 1 << 2;
+                       v16 |= DS_MODE_CLK_EDGE;
        }
        if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
                ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
@@ -368,7 +350,7 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                /* Enable RLE for long captures.
                 * Without this, captured data present errors.
                 */
-               v16 |= 1 << 3;
+               v16 |= DS_MODE_RLE_MODE;
        }
 
        WL16(&cfg.mode, v16);