SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
{
struct sr_usb_dev_inst *usb;
- usb = sdi->conn;
int ret;
- uint8_t cmd;
+ const uint8_t value = (vth / 5.0) * 255;
+ const uint16_t cmd = value | (DS_ADDR_VTH << 8);
+
+ usb = sdi->conn;
- cmd = vth/5.0 * 255;
/* Send the control command. */
- ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
- LIBUSB_ENDPOINT_OUT, DS_CMD_VTH, 0x0000, 0x0000,
- (unsigned char *)&cmd, sizeof(cmd), 3000);
+ ret = libusb_control_transfer(usb->devhdl,
+ LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
+ DS_CMD_WR_REG, 0x0000, 0x0000,
+ (unsigned char *)&cmd, sizeof(cmd), 3000);
if (ret < 0) {
sr_err("Unable to send VTH command: %s.",
libusb_error_name(ret));
ssize_t chunksize;
int transferred;
int result, ret;
- uint8_t cmd[3];
+ const uint8_t cmd[3] = {0, 0, 0};
drvc = sdi->driver->context;
usb = sdi->conn;
return result;
/* Tell the device firmware is coming. */
- memset(cmd, 0, sizeof(cmd));
if ((ret = libusb_control_transfer(usb->devhdl, LIBUSB_REQUEST_TYPE_VENDOR |
- LIBUSB_ENDPOINT_OUT, DS_CMD_FPGA_FW, 0x0000, 0x0000,
+ LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
(unsigned char *)&cmd, sizeof(cmd), USB_TIMEOUT)) < 0) {
sr_err("Failed to upload FPGA firmware: %s.", libusb_error_name(ret));
sr_resource_close(drvc->sr_ctx, &bitstream);
struct sr_trigger *trigger;
struct sr_trigger_stage *stage;
struct sr_trigger_match *match;
-
struct dev_context *devc;
- devc = sdi->priv;
const GSList *l, *m;
int channelbit, i = 0;
uint16_t v16;
+ devc = sdi->priv;
+
cfg->trig_mask0[0] = 0xffff;
cfg->trig_mask1[0] = 0xffff;
sr_dbg("configuring trigger");
- if (!(trigger = sr_session_trigger_get(sdi->session))){
+ if (!(trigger = sr_session_trigger_get(sdi->session))) {
sr_dbg("No session trigger found");
return SR_OK;
}
cfg->trig_value1[0] |= channelbit;
cfg->trig_edge0[0] |= channelbit;
cfg->trig_edge1[0] |= channelbit;
- } else if(match->match == SR_TRIGGER_EDGE){
+ } else if (match->match == SR_TRIGGER_EDGE) {
cfg->trig_edge0[0] |= channelbit;
cfg->trig_edge1[0] |= channelbit;
}
}
}
+
v16 = RL16(&cfg->mode);
v16 |= 1 << 0;
WL16(&cfg->mode, v16);
+
return SR_OK;
}
-
SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
{
struct dev_context *devc;
int transferred, len, ret;
sr_dbg("Configuring FPGA.");
+
usb = sdi->conn;
devc = sdi->priv;
LIBUSB_ENDPOINT_OUT, DS_CMD_CONFIG, 0x0000, 0x0000,
c, 3, USB_TIMEOUT);
if (ret < 0) {
- sr_err("Failed to send FPGA configure command: %s.", libusb_error_name(ret));
+ sr_err("Failed to send FPGA configure command: %s.",
+ libusb_error_name(ret));
return SR_ERR;
}
- /*
- * 15 1 = internal test mode
- * 14 1 = external test mode
- * 13 1 = loopback test mode
- * 12 1 = stream mode
- * 11 1 = serial trigger
- * 8-10 unused
- * 7 1 = analog mode
- * 6 1 = samplerate 400MHz
- * 5 1 = samplerate 200MHz or analog mode
- * 4 0 = logic, 1 = dso or analog
- * 2-3 unused
- * 1 0 = internal clock, 1 = external clock
- * 0 1 = trigger enabled
- */
v16 = 0x0000;
if (devc->dslogic_mode == DS_OP_INTERNAL_TEST)
- v16 = 1 << 15;
+ v16 = DS_MODE_INT_TEST;
else if (devc->dslogic_mode == DS_OP_EXTERNAL_TEST)
- v16 = 1 << 14;
+ v16 = DS_MODE_EXT_TEST;
else if (devc->dslogic_mode == DS_OP_LOOPBACK_TEST)
- v16 = 1 << 13;
+ v16 = DS_MODE_LPB_TEST;
if (devc->dslogic_continuous_mode)
- v16 |= 1 << 12;
- if (devc->dslogic_external_clock)
- v16 |= 1 << 1;
+ v16 |= DS_MODE_STREAM_MODE;
+ if (devc->dslogic_external_clock) {
+ v16 |= DS_MODE_CLK_TYPE;
+ if (devc->dslogic_clock_edge == DS_EDGE_FALLING)
+ v16 |= DS_MODE_CLK_EDGE;
+ }
+ if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
+ ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
+ && !devc->dslogic_continuous_mode) {
+ /* Enable RLE for long captures.
+ * Without this, captured data present errors.
+ */
+ v16 |= DS_MODE_RLE_MODE;
+ }
WL16(&cfg.mode, v16);
- v32 = ceil(SR_MHZ(100) * 1.0 / devc->cur_samplerate);
+ v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
WL32(&cfg.divider, v32);
WL32(&cfg.count, devc->limit_samples);
return SR_OK;
}
+
+static int to_bytes_per_ms(struct dev_context *devc)
+{
+ if (devc->cur_samplerate > SR_MHZ(100))
+ return SR_MHZ(100) / 1000 * (devc->sample_wide ? 2 : 1);
+
+ return devc->cur_samplerate / 1000 * (devc->sample_wide ? 2 : 1);
+}
+
+static size_t get_buffer_size(struct dev_context *devc)
+{
+ size_t s;
+
+ /*
+ * The buffer should be large enough to hold 10ms of data and
+ * a multiple of 512.
+ */
+ s = 10 * to_bytes_per_ms(devc);
+ // s = to_bytes_per_ms(devc->cur_samplerate);
+ return (s + 511) & ~511;
+}
+
+SR_PRIV int dslogic_get_number_of_transfers(struct dev_context *devc)
+{
+ unsigned int n;
+
+ /* Total buffer size should be able to hold about 100ms of data. */
+ n = (100 * to_bytes_per_ms(devc) / get_buffer_size(devc));
+ sr_info("New calculation: %d", n);
+
+ if (n > NUM_SIMUL_TRANSFERS)
+ return NUM_SIMUL_TRANSFERS;
+
+ return n;
+}
projects / libsigrok.git / blobdiff