dslogic: Fixed voltage selection

[libsigrok.git] / src / hardware / dslogic / dslogic.c

diff --git a/src/hardware/dslogic/dslogic.c b/src/hardware/dslogic/dslogic.c
index d0a98de279a6a54f1f1305a5005b4d25c48d5c67..adf197f3b557f3b2c6010f806b10d6c67ad80002 100644 (file)
--- a/src/hardware/dslogic/dslogic.c
+++ b/src/hardware/dslogic/dslogic.c
@@ -36,35 +36,13 @@
 
 #define USB_TIMEOUT (3 * 1000)
 
-SR_PRIV int dslogic_set_vth(const struct sr_dev_inst *sdi, double vth)
-{
-       struct sr_usb_dev_inst *usb;
-       int ret;
-       const uint8_t value = (vth / 5.0) * 255;
-       const uint16_t cmd = value | (DS_ADDR_VTH << 8);
-
-       usb = sdi->conn;
-
-       /* Send the control command. */
-       ret = libusb_control_transfer(usb->devhdl,
-                       LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_ENDPOINT_OUT,
-                       DS_CMD_WR_REG, 0x0000, 0x0000,
-                       (unsigned char *)&cmd, sizeof(cmd), 3000);
-       if (ret < 0) {
-               sr_err("Unable to send VTH command: %s.",
-               libusb_error_name(ret));
-               return SR_ERR;
-       }
-
-       return SR_OK;
-}
-
-SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
-               const char *name)
+SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi)
 {
+       const char *name = NULL;
        uint64_t sum;
        struct sr_resource bitstream;
        struct drv_context *drvc;
+       struct dev_context *devc;
        struct sr_usb_dev_inst *usb;
        unsigned char *buf;
        ssize_t chunksize;
@@ -73,8 +51,27 @@ SR_PRIV int dslogic_fpga_firmware_upload(const struct sr_dev_inst *sdi,
        const uint8_t cmd[3] = {0, 0, 0};
 
        drvc = sdi->driver->context;
+       devc = sdi->priv;
        usb = sdi->conn;
 
+       if (!strcmp(devc->profile->model, "DSLogic")) {
+               if (devc->cur_threshold < 1.40)
+                       name = DSLOGIC_FPGA_FIRMWARE_3V3;
+               else
+                       name = DSLOGIC_FPGA_FIRMWARE_5V;
+       } else if (!strcmp(devc->profile->model, "DSLogic Pro")){
+               name = DSLOGIC_PRO_FPGA_FIRMWARE;
+       } else if (!strcmp(devc->profile->model, "DSLogic Plus")){
+               name = DSLOGIC_PLUS_FPGA_FIRMWARE;
+       } else if (!strcmp(devc->profile->model, "DSLogic Basic")){
+               name = DSLOGIC_BASIC_FPGA_FIRMWARE;
+       } else if (!strcmp(devc->profile->model, "DSCope")) {
+               name = DSCOPE_FPGA_FIRMWARE;
+       } else {
+               sr_err("Failed to select FPGA firmware.");
+               return SR_ERR;
+       }
+
        sr_dbg("Uploading FPGA firmware '%s'.", name);
 
        result = sr_resource_open(drvc->sr_ctx, &bitstream,
@@ -325,6 +322,12 @@ SR_PRIV int dslogic_fpga_configure(const struct sr_dev_inst *sdi)
                v16 = DS_MODE_EXT_TEST;
        else if (devc->mode == DS_OP_LOOPBACK_TEST)
                v16 = DS_MODE_LPB_TEST;
+
+       if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
+               v16 |= DS_MODE_HALF_MODE;
+       else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
+               v16 |= DS_MODE_QUAR_MODE;
+
        if (devc->continuous_mode)
                v16 |= DS_MODE_STREAM_MODE;
        if (devc->external_clock) {