#include <config.h>
#include <math.h>
+#include <stdbool.h>
#include <glib.h>
#include <glib/gstdio.h>
#include "protocol.h"
/*
* Get the session trigger and configure the FPGA structure
* accordingly.
+ * @return @c true if any triggers are enabled, @c false otherwise.
*/
-static void set_trigger(const struct sr_dev_inst *sdi, struct fpga_config *cfg)
+static bool set_trigger(const struct sr_dev_inst *sdi, struct fpga_config *cfg)
{
struct sr_trigger *trigger;
struct sr_trigger_stage *stage;
if (!(trigger = sr_session_trigger_get(sdi->session))) {
sr_dbg("No session trigger found");
- return;
+ return false;
}
for (l = trigger->stages; l; l = l->next) {
}
cfg->trig_glb = (num_enabled_channels << 4) | (num_trigger_stages - 1);
+
+ return num_trigger_stages != 0;
}
static int fpga_configure(const struct sr_dev_inst *sdi)
{
- struct dev_context *devc;
- struct sr_usb_dev_inst *usb;
+ const struct dev_context *const devc = sdi->priv;
+ const struct sr_usb_dev_inst *const usb = sdi->conn;
uint8_t c[3];
struct fpga_config cfg;
- uint16_t v16;
- uint32_t v32;
+ uint16_t mode = 0;
+ uint32_t divider;
int transferred, len, ret;
sr_dbg("Configuring FPGA.");
- usb = sdi->conn;
- devc = sdi->priv;
-
WL32(&cfg.sync, DS_CFG_START);
WL16(&cfg.mode_header, DS_CFG_MODE);
WL16(&cfg.divider_header, DS_CFG_DIVIDER);
return SR_ERR;
}
- v16 = 0x0000;
+ if (set_trigger(sdi, &cfg))
+ mode |= DS_MODE_TRIG_EN;
if (devc->mode == DS_OP_INTERNAL_TEST)
- v16 = DS_MODE_INT_TEST;
+ mode |= DS_MODE_INT_TEST;
else if (devc->mode == DS_OP_EXTERNAL_TEST)
- v16 = DS_MODE_EXT_TEST;
+ mode |= DS_MODE_EXT_TEST;
else if (devc->mode == DS_OP_LOOPBACK_TEST)
- v16 = DS_MODE_LPB_TEST;
+ mode |= DS_MODE_LPB_TEST;
if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 2)
- v16 |= DS_MODE_HALF_MODE;
+ mode |= DS_MODE_HALF_MODE;
else if (devc->cur_samplerate == DS_MAX_LOGIC_SAMPLERATE * 4)
- v16 |= DS_MODE_QUAR_MODE;
+ mode |= DS_MODE_QUAR_MODE;
if (devc->continuous_mode)
- v16 |= DS_MODE_STREAM_MODE;
+ mode |= DS_MODE_STREAM_MODE;
if (devc->external_clock) {
- v16 |= DS_MODE_CLK_TYPE;
+ mode |= DS_MODE_CLK_TYPE;
if (devc->clock_edge == DS_EDGE_FALLING)
- v16 |= DS_MODE_CLK_EDGE;
+ mode |= DS_MODE_CLK_EDGE;
}
if (devc->limit_samples > DS_MAX_LOGIC_DEPTH *
ceil(devc->cur_samplerate * 1.0 / DS_MAX_LOGIC_SAMPLERATE)
/* Enable RLE for long captures.
* Without this, captured data present errors.
*/
- v16 |= DS_MODE_RLE_MODE;
+ mode |= DS_MODE_RLE_MODE;
}
- WL16(&cfg.mode, v16);
- v32 = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
- WL32(&cfg.divider, v32);
+ WL16(&cfg.mode, mode);
+ divider = ceil(DS_MAX_LOGIC_SAMPLERATE * 1.0 / devc->cur_samplerate);
+ WL32(&cfg.divider, divider);
/* Number of 16-sample units. */
WL32(&cfg.count, devc->limit_samples / 16);
- set_trigger(sdi, &cfg);
-
len = sizeof(struct fpga_config);
ret = libusb_bulk_transfer(usb->devhdl, 2 | LIBUSB_ENDPOINT_OUT,
(unsigned char *)&cfg, len, &transferred, USB_TIMEOUT);
if ((sdi->status == SR_ST_INITIALIZING) ||
(sdi->status == SR_ST_INACTIVE)) {
/* Check device by its physical USB bus/port address. */
- usb_get_port_path(devlist[i], connection_id, sizeof(connection_id));
+ if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
+ continue;
+
if (strcmp(sdi->connection_id, connection_id))
/* This is not the one. */
continue;
for (int bit = 0; bit != 64; bit++) {
const uint64_t *word_ptr = src_ptr;
sample = 0;
- for (size_t channel = 0; channel != channel_count;
+ for (unsigned int channel = 0; channel != 16;
channel++) {
- if ((channel_mask & (1 << channel)) &&
- (*word_ptr++ & (1ULL << bit)))
+ const uint16_t m = channel_mask >> channel;
+ if (!m)
+ break;
+ if ((m & 1) && ((*word_ptr++ >> bit) & UINT64_C(1)))
sample |= 1 << channel;
}
*dst_ptr++ = sample;
*/
const size_t block_size = enabled_channel_count(sdi) * 512;
const size_t s = 10 * to_bytes_per_ms(sdi);
+ if (!block_size)
+ return s;
return ((s + block_size - 1) / block_size) * block_size;
}