SR_CONF_CLOCK_EDGE | SR_CONF_GET | SR_CONF_SET | SR_CONF_LIST,
};
-static const char *signal_edge_names[] = {
+static const int32_t trigger_matches[] = {
+ SR_TRIGGER_ZERO,
+ SR_TRIGGER_ONE,
+ SR_TRIGGER_RISING,
+ SR_TRIGGER_FALLING,
+ SR_TRIGGER_EDGE,
+};
+
+static const char *signal_edges[] = {
[DS_EDGE_RISING] = "rising",
[DS_EDGE_FALLING] = "falling",
};
-static const double voltage_thresholds[][2] = {
+static const double thresholds[][2] = {
{ 0.7, 1.4 },
{ 1.4, 3.6 },
};
continue;
}
- usb_get_port_path(devlist[i], connection_id, sizeof(connection_id));
-
libusb_close(hdl);
+ if (usb_get_port_path(devlist[i], connection_id, sizeof(connection_id)) < 0)
+ continue;
+
prof = NULL;
for (j = 0; supported_device[j].vid; j++) {
if (des.idVendor == supported_device[j].vid &&
/* Logic channels, all in one channel group. */
cg = g_malloc0(sizeof(struct sr_channel_group));
cg->name = g_strdup("Logic");
- for (j = 0; j < 16; j++) {
+ for (j = 0; j < NUM_CHANNELS; j++) {
sprintf(channel_name, "%d", j);
ch = sr_channel_new(sdi, j, SR_CHANNEL_LOGIC,
TRUE, channel_name);
devc->cur_samplerate = devc->samplerates[0];
}
- if (devc->cur_threshold == 0.0)
- devc->cur_threshold = 1.5;
+ if (devc->cur_threshold == 0.0) {
+ devc->cur_threshold = thresholds[1][0];
+ return dslogic_set_voltage_threshold(sdi, devc->cur_threshold);
+ }
return SR_OK;
}
case SR_CONF_VOLTAGE_THRESHOLD:
if (!strcmp(devc->profile->model, "DSLogic")) {
if ((idx = std_double_tuple_idx_d0(devc->cur_threshold,
- ARRAY_AND_SIZE(voltage_thresholds))) < 0)
+ ARRAY_AND_SIZE(thresholds))) < 0)
return SR_ERR_BUG;
- *data = std_gvar_tuple_double(voltage_thresholds[idx][0],
- voltage_thresholds[idx][1]);
+ *data = std_gvar_tuple_double(thresholds[idx][0],
+ thresholds[idx][1]);
} else {
*data = std_gvar_tuple_double(devc->cur_threshold, devc->cur_threshold);
}
break;
case SR_CONF_CLOCK_EDGE:
idx = devc->clock_edge;
- if (idx >= (int)ARRAY_SIZE(signal_edge_names))
+ if (idx >= (int)ARRAY_SIZE(signal_edges))
return SR_ERR_BUG;
- *data = g_variant_new_string(signal_edge_names[0]);
+ *data = g_variant_new_string(signal_edges[0]);
break;
default:
return SR_ERR_NA;
break;
case SR_CONF_CAPTURE_RATIO:
devc->capture_ratio = g_variant_get_uint64(data);
- return (devc->capture_ratio > 100) ? SR_ERR : SR_OK;
+ break;
case SR_CONF_VOLTAGE_THRESHOLD:
if (!strcmp(devc->profile->model, "DSLogic")) {
- if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(voltage_thresholds))) < 0)
+ if ((idx = std_double_tuple_idx(data, ARRAY_AND_SIZE(thresholds))) < 0)
return SR_ERR_ARG;
- devc->cur_threshold = voltage_thresholds[idx][0];
+ devc->cur_threshold = thresholds[idx][0];
return dslogic_fpga_firmware_upload(sdi);
} else {
g_variant_get(data, "(dd)", &low, &high);
devc->continuous_mode = g_variant_get_boolean(data);
break;
case SR_CONF_CLOCK_EDGE:
- if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edge_names))) < 0)
+ if ((idx = std_str_idx(data, ARRAY_AND_SIZE(signal_edges))) < 0)
return SR_ERR_ARG;
devc->clock_edge = idx;
break;
case SR_CONF_DEVICE_OPTIONS:
return STD_CONFIG_LIST(key, data, sdi, cg, scanopts, drvopts, devopts);
case SR_CONF_VOLTAGE_THRESHOLD:
+ if (!devc || !devc->profile)
+ return SR_ERR_ARG;
if (!strcmp(devc->profile->model, "DSLogic"))
- *data = std_gvar_thresholds(ARRAY_AND_SIZE(voltage_thresholds));
+ *data = std_gvar_thresholds(ARRAY_AND_SIZE(thresholds));
else
*data = std_gvar_min_max_step_thresholds(0.0, 5.0, 0.1);
break;
case SR_CONF_SAMPLERATE:
+ if (!devc)
+ return SR_ERR_ARG;
*data = std_gvar_samplerates(devc->samplerates, devc->num_samplerates);
break;
+ case SR_CONF_TRIGGER_MATCH:
+ *data = std_gvar_array_i32(ARRAY_AND_SIZE(trigger_matches));
+ break;
case SR_CONF_CLOCK_EDGE:
- *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edge_names));
+ *data = g_variant_new_strv(ARRAY_AND_SIZE(signal_edges));
break;
default:
return SR_ERR_NA;