asix-sigma: rework outer sample download loop (DRAM lines iteration)

[libsigrok.git] / src / hardware / asix-sigma / protocol.h

diff --git a/src/hardware/asix-sigma/protocol.h b/src/hardware/asix-sigma/protocol.h
index 83c6adb93f2b8564b2a099f8640e6731317dcfd4..9fcbdd30f75f21a603a7ffdcf83f5a53570d45ed 100644 (file)
--- a/src/hardware/asix-sigma/protocol.h
+++ b/src/hardware/asix-sigma/protocol.h
@@ -359,12 +359,24 @@ struct dev_context {
                struct sr_sw_limits submit;
        } limit;
        enum sigma_firmware_idx firmware_idx;
-       struct {
+       struct sigma_sample_interp {
                /* Interpretation of sample memory. */
                size_t num_channels;
                size_t samples_per_event;
-               uint16_t lastts;
-               uint16_t lastsample;
+               struct {
+                       uint16_t ts;
+                       uint16_t sample;
+               } last;
+               struct sigma_location {
+                       size_t raw, line, cluster, event;
+               } start, stop, trig, iter;
+               struct {
+                       size_t lines_total, lines_done;
+                       size_t lines_per_read; /* USB transfer limit */
+                       size_t lines_rcvd;
+                       struct sigma_dram_line *rcvd_lines;
+                       struct sigma_dram_line *curr_line;
+               } fetch;
        } interp;
        uint64_t capture_ratio;
        struct sigma_trigger trigger;