SR_PRIV const size_t samplerates_count = ARRAY_SIZE(samplerates);
-static const char firmware_files[][24] = {
- /* 50 MHz, supports 8 bit fractions */
- "asix-sigma-50.fw",
- /* 100 MHz */
- "asix-sigma-100.fw",
- /* 200 MHz */
- "asix-sigma-200.fw",
- /* Synchronous clock from pin */
- "asix-sigma-50sync.fw",
- /* Frequency counter */
- "asix-sigma-phasor.fw",
+static const char *firmware_files[] = {
+ "asix-sigma-50.fw", /* Up to 50MHz sample rate, 8bit divider. */
+ "asix-sigma-100.fw", /* 100MHz sample rate, fixed. */
+ "asix-sigma-200.fw", /* 200MHz sample rate, fixed. */
+ "asix-sigma-50sync.fw", /* Synchronous clock from external pin. */
+ "asix-sigma-phasor.fw", /* Frequency counter. */
};
+#define SIGMA_FIRMWARE_SIZE_LIMIT (256 * 1024)
+
static int sigma_read(void *buf, size_t size, struct dev_context *devc)
{
int ret;
static int sigma_read_pos(uint32_t *stoppos, uint32_t *triggerpos,
struct dev_context *devc)
{
+ /*
+ * Read 6 registers starting at trigger position LSB.
+ * Which yields two 24bit counter values.
+ */
uint8_t buf[] = {
REG_ADDR_LOW | READ_TRIGGER_POS_LOW,
-
- REG_READ_ADDR | NEXT_REG,
- REG_READ_ADDR | NEXT_REG,
- REG_READ_ADDR | NEXT_REG,
- REG_READ_ADDR | NEXT_REG,
- REG_READ_ADDR | NEXT_REG,
- REG_READ_ADDR | NEXT_REG,
+ REG_READ_ADDR | REG_ADDR_INC,
+ REG_READ_ADDR | REG_ADDR_INC,
+ REG_READ_ADDR | REG_ADDR_INC,
+ REG_READ_ADDR | REG_ADDR_INC,
+ REG_READ_ADDR | REG_ADDR_INC,
+ REG_READ_ADDR | REG_ADDR_INC,
};
uint8_t result[6];
* chunks with meta data in the upper 64 bytes. Thus when the
* decrements takes us into this upper part of the chunk, then
* further move backwards to the end of the chunk's data part.
+ *
+ * TODO Re-consider the above comment's validity. It's true
+ * that a 1024byte row contains 512 u16 entities, of which 64
+ * are timestamps and 448 are events with sample data. It's not
+ * true that 64bytes of metadata reside at the top of a 512byte
+ * block in a row.
+ *
+ * TODO Use ROW_MASK and CLUSTERS_PER_ROW here?
*/
if ((--*stoppos & 0x1ff) == 0x1ff)
*stoppos -= 64;
static int sigma_read_dram(uint16_t startchunk, size_t numchunks,
uint8_t *data, struct dev_context *devc)
{
- size_t i;
uint8_t buf[4096];
int idx;
+ size_t chunk;
+ int sel;
+ gboolean is_last;
- /* Send the startchunk. Index start with 1. */
+ /* Communicate DRAM start address (memory row, aka samples line). */
idx = 0;
buf[idx++] = startchunk >> 8;
buf[idx++] = startchunk & 0xff;
sigma_write_register(WRITE_MEMROW, buf, idx, devc);
- /* Read the DRAM. */
+ /*
+ * Access DRAM content. Fetch from DRAM to FPGA's internal RAM,
+ * then transfer via USB. Interleave the FPGA's DRAM access and
+ * USB transfer, use alternating buffers (0/1) in the process.
+ */
idx = 0;
buf[idx++] = REG_DRAM_BLOCK;
buf[idx++] = REG_DRAM_WAIT_ACK;
-
- for (i = 0; i < numchunks; i++) {
- /* Alternate bit to copy from DRAM to cache. */
- if (i != (numchunks - 1))
- buf[idx++] = REG_DRAM_BLOCK | (((i + 1) % 2) << 4);
-
- buf[idx++] = REG_DRAM_BLOCK_DATA | ((i % 2) << 4);
-
- if (i != (numchunks - 1))
+ for (chunk = 0; chunk < numchunks; chunk++) {
+ sel = chunk % 2;
+ is_last = chunk == numchunks - 1;
+ if (!is_last)
+ buf[idx++] = REG_DRAM_BLOCK | REG_DRAM_SEL_BOOL(!sel);
+ buf[idx++] = REG_DRAM_BLOCK_DATA | REG_DRAM_SEL_BOOL(sel);
+ if (!is_last)
buf[idx++] = REG_DRAM_WAIT_ACK;
}
-
sigma_write(buf, idx, devc);
- return sigma_read(data, numchunks * CHUNK_SIZE, devc);
+ return sigma_read(data, numchunks * ROW_LENGTH_BYTES, devc);
}
/* Upload trigger look-up tables to Sigma. */
if (lut->m1d[3] & bit)
tmp[1] |= 0x80;
- sigma_write_register(WRITE_TRIGGER_SELECT0, tmp, sizeof(tmp),
+ sigma_write_register(WRITE_TRIGGER_SELECT, tmp, sizeof(tmp),
devc);
- sigma_set_register(WRITE_TRIGGER_SELECT1, 0x30 | i, devc);
+ sigma_set_register(WRITE_TRIGGER_SELECT2, 0x30 | i, devc);
}
/* Send the parameters */
- sigma_write_register(WRITE_TRIGGER_SELECT0, (uint8_t *) &lut->params,
+ sigma_write_register(WRITE_TRIGGER_SELECT, (uint8_t *) &lut->params,
sizeof(lut->params), devc);
return SR_OK;
}
/*
- * Configure the FPGA for bitbang mode.
- * This sequence is documented in section 2. of the ASIX Sigma programming
- * manual. This sequence is necessary to configure the FPGA in the Sigma
- * into Bitbang mode, in which it can be programmed with the firmware.
+ * See Xilinx UG332 for Spartan-3 FPGA configuration. The SIGMA device
+ * uses FTDI bitbang mode for netlist download in slave serial mode.
+ * (LATER: The OMEGA device's cable contains a more capable FTDI chip
+ * and uses MPSSE mode for bitbang. -- Can we also use FT232H in FT245
+ * compatible bitbang mode? For maximum code re-use and reduced libftdi
+ * dependency? See section 3.5.5 of FT232H: D0 clk, D1 data (out), D2
+ * data (in), D3 select, D4-7 GPIOL. See section 3.5.7 for MCU FIFO.)
+ *
+ * 750kbps rate (four times the speed of sigmalogan) works well for
+ * netlist download. All pins except INIT_B are output pins during
+ * configuration download.
+ *
+ * Some pins are inverted as a byproduct of level shifting circuitry.
+ * That's why high CCLK level (from the cable's point of view) is idle
+ * from the FPGA's perspective.
+ *
+ * The vendor's literature discusses a "suicide sequence" which ends
+ * regular FPGA execution and should be sent before entering bitbang
+ * mode and sending configuration data. Set D7 and toggle D2, D3, D4
+ * a few times.
+ */
+#define BB_PIN_CCLK (1 << 0) /* D0, CCLK */
+#define BB_PIN_PROG (1 << 1) /* D1, PROG */
+#define BB_PIN_D2 (1 << 2) /* D2, (part of) SUICIDE */
+#define BB_PIN_D3 (1 << 3) /* D3, (part of) SUICIDE */
+#define BB_PIN_D4 (1 << 4) /* D4, (part of) SUICIDE (unused?) */
+#define BB_PIN_INIT (1 << 5) /* D5, INIT, input pin */
+#define BB_PIN_DIN (1 << 6) /* D6, DIN */
+#define BB_PIN_D7 (1 << 7) /* D7, (part of) SUICIDE */
+
+#define BB_BITRATE (750 * 1000)
+#define BB_PINMASK (0xff & ~BB_PIN_INIT)
+
+/*
+ * Initiate slave serial mode for configuration download. Which is done
+ * by pulsing PROG_B and sensing INIT_B. Make sure CCLK is idle before
+ * initiating the configuration download. Run a "suicide sequence" first
+ * to terminate the regular FPGA operation before reconfiguration.
*/
static int sigma_fpga_init_bitbang(struct dev_context *devc)
{
uint8_t suicide[] = {
- 0x84, 0x84, 0x88, 0x84, 0x88, 0x84, 0x88, 0x84,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D3,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D3,
+ BB_PIN_D7 | BB_PIN_D2,
+ BB_PIN_D7 | BB_PIN_D3,
+ BB_PIN_D7 | BB_PIN_D2,
};
uint8_t init_array[] = {
- 0x01, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
- 0x01, 0x01,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK | BB_PIN_PROG,
+ BB_PIN_CCLK | BB_PIN_PROG,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
+ BB_PIN_CCLK,
};
- int i, ret, timeout = (10 * 1000);
+ int retries, ret;
uint8_t data;
/* Section 2. part 1), do the FPGA suicide. */
sigma_write(suicide, sizeof(suicide), devc);
sigma_write(suicide, sizeof(suicide), devc);
- /* Section 2. part 2), do pulse on D1. */
+ /* Section 2. part 2), pulse PROG. */
sigma_write(init_array, sizeof(init_array), devc);
ftdi_usb_purge_buffers(&devc->ftdic);
- /* Wait until the FPGA asserts D6/INIT_B. */
- for (i = 0; i < timeout; i++) {
+ /* Wait until the FPGA asserts INIT_B. */
+ retries = 10;
+ while (retries--) {
ret = sigma_read(&data, 1, devc);
if (ret < 0)
return ret;
- /* Test if pin D6 got asserted. */
- if (data & (1 << 5))
- return 0;
- /* The D6 was not asserted yet, wait a bit. */
+ if (data & BB_PIN_INIT)
+ return SR_OK;
g_usleep(10 * 1000);
}
*/
static int sigma_fpga_init_la(struct dev_context *devc)
{
- /* Initialize the logic analyzer mode. */
+ /*
+ * TODO Construct the sequence at runtime? Such that request data
+ * and response check values will match more apparently?
+ */
uint8_t mode_regval = WMR_SDRAMINIT;
uint8_t logic_mode_start[] = {
+ /* Read ID register. */
REG_ADDR_LOW | (READ_ID & 0xf),
REG_ADDR_HIGH | (READ_ID >> 4),
- REG_READ_ADDR, /* Read ID register. */
+ REG_READ_ADDR,
+ /* Write 0x55 to scratch register, read back. */
REG_ADDR_LOW | (WRITE_TEST & 0xf),
REG_DATA_LOW | 0x5,
REG_DATA_HIGH_WRITE | 0x5,
- REG_READ_ADDR, /* Read scratch register. */
+ REG_READ_ADDR,
+ /* Write 0xaa to scratch register, read back. */
REG_DATA_LOW | 0xa,
REG_DATA_HIGH_WRITE | 0xa,
- REG_READ_ADDR, /* Read scratch register. */
+ REG_READ_ADDR,
+ /* Initiate SDRAM initialization in mode register. */
REG_ADDR_LOW | (WRITE_MODE & 0xf),
REG_DATA_LOW | (mode_regval & 0xf),
REG_DATA_HIGH_WRITE | (mode_regval >> 4),
};
-
uint8_t result[3];
int ret;
- /* Initialize the logic analyzer mode. */
+ /*
+ * Send the command sequence which contains 3 READ requests.
+ * Expect to see the corresponding 3 response bytes.
+ */
sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
-
- /* Expect a 3 byte reply since we issued three READ requests. */
- ret = sigma_read(result, 3, devc);
- if (ret != 3)
+ ret = sigma_read(result, ARRAY_SIZE(result), devc);
+ if (ret != ARRAY_SIZE(result))
goto err;
-
if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
goto err;
return SR_OK;
+
err:
sr_err("Configuration failed. Invalid reply received.");
return SR_ERR;
static int sigma_fw_2_bitbang(struct sr_context *ctx, const char *name,
uint8_t **bb_cmd, gsize *bb_cmd_size)
{
- size_t i, file_size, bb_size;
- char *firmware;
- uint8_t *bb_stream, *bbs;
+ uint8_t *firmware;
+ size_t file_size;
+ uint8_t *p;
+ size_t l;
uint32_t imm;
- int bit, v;
- int ret = SR_OK;
+ size_t bb_size;
+ uint8_t *bb_stream, *bbs, byte, mask, v;
/* Retrieve the on-disk firmware file content. */
- firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE,
- name, &file_size, 256 * 1024);
+ firmware = sr_resource_load(ctx, SR_RESOURCE_FIRMWARE, name,
+ &file_size, SIGMA_FIRMWARE_SIZE_LIMIT);
if (!firmware)
- return SR_ERR;
+ return SR_ERR_IO;
/* Unscramble the file content (XOR with "random" sequence). */
+ p = firmware;
+ l = file_size;
imm = 0x3f6df2ab;
- for (i = 0; i < file_size; i++) {
+ while (l--) {
imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
- firmware[i] ^= imm & 0xff;
+ *p++ ^= imm & 0xff;
}
/*
* the bitbang samples, and release the allocated memory.
*/
bb_size = file_size * 8 * 2;
- bb_stream = (uint8_t *)g_try_malloc(bb_size);
+ bb_stream = g_try_malloc(bb_size);
if (!bb_stream) {
sr_err("%s: Failed to allocate bitbang stream", __func__);
- ret = SR_ERR_MALLOC;
- goto exit;
+ g_free(firmware);
+ return SR_ERR_MALLOC;
}
bbs = bb_stream;
- for (i = 0; i < file_size; i++) {
- for (bit = 7; bit >= 0; bit--) {
- v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
- *bbs++ = v | 0x01;
+ p = firmware;
+ l = file_size;
+ while (l--) {
+ byte = *p++;
+ mask = 0x80;
+ while (mask) {
+ v = (byte & mask) ? BB_PIN_DIN : 0;
+ mask >>= 1;
+ *bbs++ = v | BB_PIN_CCLK;
*bbs++ = v;
}
}
+ g_free(firmware);
/* The transformation completed successfully, return the result. */
*bb_cmd = bb_stream;
*bb_cmd_size = bb_size;
-exit:
- g_free(firmware);
- return ret;
+ return SR_OK;
}
static int upload_firmware(struct sr_context *ctx,
return SR_OK;
}
- ret = ftdi_set_bitmode(&devc->ftdic, 0xdf, BITMODE_BITBANG);
+ /* Set the cable to bitbang mode. */
+ ret = ftdi_set_bitmode(&devc->ftdic, BB_PINMASK, BITMODE_BITBANG);
if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
ftdi_get_error_string(&devc->ftdic));
return SR_ERR;
}
-
- /* Four times the speed of sigmalogan - Works well. */
- ret = ftdi_set_baudrate(&devc->ftdic, 750 * 1000);
+ ret = ftdi_set_baudrate(&devc->ftdic, BB_BITRATE);
if (ret < 0) {
sr_err("ftdi_set_baudrate failed: %s",
ftdi_get_error_string(&devc->ftdic));
return SR_ERR;
}
- /* Initialize the FPGA for firmware upload. */
+ /* Initiate FPGA configuration mode. */
ret = sigma_fpga_init_bitbang(devc);
if (ret)
return ret;
- /* Prepare firmware. */
+ /* Prepare wire format of the firmware image. */
ret = sigma_fw_2_bitbang(ctx, firmware, &buf, &buf_size);
if (ret != SR_OK) {
sr_err("An error occurred while reading the firmware: %s",
return ret;
}
- /* Upload firmware. */
+ /* Write the FPGA netlist to the cable. */
sr_info("Uploading firmware file '%s'.", firmware);
sigma_write(buf, buf_size, devc);
g_free(buf);
- ret = ftdi_set_bitmode(&devc->ftdic, 0x00, BITMODE_RESET);
+ /* Leave bitbang mode and discard pending input data. */
+ ret = ftdi_set_bitmode(&devc->ftdic, 0, BITMODE_RESET);
if (ret < 0) {
sr_err("ftdi_set_bitmode failed: %s",
ftdi_get_error_string(&devc->ftdic));
return SR_ERR;
}
-
ftdi_usb_purge_buffers(&devc->ftdic);
-
- /* Discard garbage. */
while (sigma_read(&pins, 1, devc) == 1)
;
if (ret != SR_OK)
return ret;
+ /* Keep track of successful firmware download completion. */
devc->cur_firmware = firmware_idx;
-
sr_info("Firmware uploaded.");
return SR_OK;
return ret;
}
+/*
+ * Arrange for a session feed submit buffer. A queue where a number of
+ * samples gets accumulated to reduce the number of send calls. Which
+ * also enforces an optional sample count limit for data acquisition.
+ *
+ * The buffer holds up to CHUNK_SIZE bytes. The unit size is fixed (the
+ * driver provides a fixed channel layout regardless of samplerate).
+ */
+
+#define CHUNK_SIZE (4 * 1024 * 1024)
+
+struct submit_buffer {
+ size_t unit_size;
+ size_t max_samples, curr_samples;
+ uint8_t *sample_data;
+ uint8_t *write_pointer;
+ struct sr_dev_inst *sdi;
+ struct sr_datafeed_packet packet;
+ struct sr_datafeed_logic logic;
+ struct sr_sw_limits limit_samples;
+};
+
+static int alloc_submit_buffer(struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc;
+ struct submit_buffer *buffer;
+ size_t size;
+
+ devc = sdi->priv;
+
+ buffer = g_malloc0(sizeof(*buffer));
+ devc->buffer = buffer;
+
+ buffer->unit_size = sizeof(uint16_t);
+ size = CHUNK_SIZE;
+ size /= buffer->unit_size;
+ buffer->max_samples = size;
+ size *= buffer->unit_size;
+ buffer->sample_data = g_try_malloc0(size);
+ if (!buffer->sample_data)
+ return SR_ERR_MALLOC;
+ buffer->write_pointer = buffer->sample_data;
+ sr_sw_limits_init(&buffer->limit_samples);
+
+ buffer->sdi = sdi;
+ memset(&buffer->logic, 0, sizeof(buffer->logic));
+ buffer->logic.unitsize = buffer->unit_size;
+ buffer->logic.data = buffer->sample_data;
+ memset(&buffer->packet, 0, sizeof(buffer->packet));
+ buffer->packet.type = SR_DF_LOGIC;
+ buffer->packet.payload = &buffer->logic;
+
+ return SR_OK;
+}
+
+static int setup_submit_buffer(struct dev_context *devc)
+{
+ struct submit_buffer *buffer;
+ int ret;
+ GVariant *data;
+ uint64_t total;
+
+ buffer = devc->buffer;
+
+ total = devc->limit_samples;
+ if (total) {
+ data = g_variant_new_uint64(total);
+ ret = sr_sw_limits_config_set(&buffer->limit_samples,
+ SR_CONF_LIMIT_SAMPLES, data);
+ g_variant_unref(data);
+ if (ret != SR_OK)
+ return ret;
+ }
+
+ sr_sw_limits_acquisition_start(&buffer->limit_samples);
+
+ return SR_OK;
+}
+
+static void free_submit_buffer(struct dev_context *devc)
+{
+ struct submit_buffer *buffer;
+
+ if (!devc)
+ return;
+
+ buffer = devc->buffer;
+ if (!buffer)
+ return;
+ devc->buffer = NULL;
+
+ g_free(buffer->sample_data);
+ g_free(buffer);
+}
+
+static int flush_submit_buffer(struct dev_context *devc)
+{
+ struct submit_buffer *buffer;
+ int ret;
+
+ buffer = devc->buffer;
+
+ /* Is queued sample data available? */
+ if (!buffer->curr_samples)
+ return SR_OK;
+
+ /* Submit to the session feed. */
+ buffer->logic.length = buffer->curr_samples * buffer->unit_size;
+ ret = sr_session_send(buffer->sdi, &buffer->packet);
+ if (ret != SR_OK)
+ return ret;
+
+ /* Rewind queue position. */
+ buffer->curr_samples = 0;
+ buffer->write_pointer = buffer->sample_data;
+
+ return SR_OK;
+}
+
+static int addto_submit_buffer(struct dev_context *devc,
+ uint16_t sample, size_t count)
+{
+ struct submit_buffer *buffer;
+ int ret;
+
+ buffer = devc->buffer;
+ if (sr_sw_limits_check(&buffer->limit_samples))
+ count = 0;
+
+ /*
+ * Individually accumulate and check each sample, such that
+ * accumulation between flushes won't exceed local storage, and
+ * enforcement of user specified limits is exact.
+ */
+ while (count--) {
+ WL16(buffer->write_pointer, sample);
+ buffer->write_pointer += buffer->unit_size;
+ buffer->curr_samples++;
+ if (buffer->curr_samples == buffer->max_samples) {
+ ret = flush_submit_buffer(devc);
+ if (ret != SR_OK)
+ return ret;
+ }
+ sr_sw_limits_update_samples_read(&buffer->limit_samples, 1);
+ if (sr_sw_limits_check(&buffer->limit_samples))
+ break;
+ }
+
+ return SR_OK;
+}
+
/*
* In 100 and 200 MHz mode, only a single pin rising/falling can be
* set as trigger. In other modes, two rising/falling triggers can be set,
return i & 0x7;
}
+static gboolean sample_matches_trigger(struct dev_context *devc, uint16_t sample)
+{
+ /* TODO
+ * Check whether the combination of this very sample and the
+ * previous state match the configured trigger condition. This
+ * improves the resolution of the trigger marker's position.
+ * The hardware provided position is coarse, and may point to
+ * a position before the actual match.
+ *
+ * See the previous get_trigger_offset() implementation. This
+ * code needs to get re-used here.
+ */
+ (void)devc;
+ (void)sample;
+ (void)get_trigger_offset;
+
+ return FALSE;
+}
+
+static int check_and_submit_sample(struct dev_context *devc,
+ uint16_t sample, size_t count, gboolean check_trigger)
+{
+ gboolean triggered;
+ int ret;
+
+ triggered = check_trigger && sample_matches_trigger(devc, sample);
+ if (triggered) {
+ ret = flush_submit_buffer(devc);
+ if (ret != SR_OK)
+ return ret;
+ ret = std_session_send_df_trigger(devc->buffer->sdi);
+ if (ret != SR_OK)
+ return ret;
+ }
+
+ ret = addto_submit_buffer(devc, sample, count);
+ if (ret != SR_OK)
+ return ret;
+
+ return SR_OK;
+}
+
/*
* Return the timestamp of "DRAM cluster".
*/
return outdata;
}
-static void store_sr_sample(uint8_t *samples, int idx, uint16_t data)
-{
- samples[2 * idx + 0] = (data >> 0) & 0xff;
- samples[2 * idx + 1] = (data >> 8) & 0xff;
-}
-
-/*
- * Local wrapper around sr_session_send() calls. Make sure to not send
- * more samples to the session's datafeed than what was requested by a
- * previously configured (optional) sample count.
- */
-static void sigma_session_send(struct sr_dev_inst *sdi,
- struct sr_datafeed_packet *packet)
-{
- struct dev_context *devc;
- struct sr_datafeed_logic *logic;
- uint64_t send_now;
-
- devc = sdi->priv;
- if (devc->limit_samples) {
- logic = (void *)packet->payload;
- send_now = logic->length / logic->unitsize;
- if (devc->sent_samples + send_now > devc->limit_samples) {
- send_now = devc->limit_samples - devc->sent_samples;
- logic->length = send_now * logic->unitsize;
- }
- if (!send_now)
- return;
- devc->sent_samples += send_now;
- }
-
- sr_session_send(sdi, packet);
-}
-
-/*
- * This size translates to: event count (1K events per cluster), times
- * the sample width (unitsize, 16bits per event), times the maximum
- * number of samples per event.
- */
-#define SAMPLES_BUFFER_SIZE (1024 * 2 * 4)
-
-static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
- unsigned int events_in_cluster,
- unsigned int triggered,
- struct sr_dev_inst *sdi)
+static void sigma_decode_dram_cluster(struct dev_context *devc,
+ struct sigma_dram_cluster *dram_cluster,
+ size_t events_in_cluster, gboolean triggered)
{
- struct dev_context *devc = sdi->priv;
- struct sigma_state *ss = &devc->state;
- struct sr_datafeed_packet packet;
- struct sr_datafeed_logic logic;
+ struct sigma_state *ss;
uint16_t tsdiff, ts, sample, item16;
- uint8_t samples[SAMPLES_BUFFER_SIZE];
- uint8_t *send_ptr;
- size_t send_count, trig_count;
unsigned int i;
- int j;
- ts = sigma_dram_cluster_ts(dram_cluster);
- tsdiff = ts - ss->lastts;
- ss->lastts = ts + EVENTS_PER_CLUSTER;
-
- packet.type = SR_DF_LOGIC;
- packet.payload = &logic;
- logic.unitsize = 2;
- logic.data = samples;
+ if (!devc->use_triggers || !ASIX_SIGMA_WITH_TRIGGER)
+ triggered = FALSE;
/*
* If this cluster is not adjacent to the previously received
* cluster, then send the appropriate number of samples with the
* previous values to the sigrok session. This "decodes RLE".
+ *
+ * These samples cannot match the trigger since they just repeat
+ * the previously submitted data pattern. (This assumption holds
+ * for simple level and edge triggers. It would not for timed or
+ * counted conditions, which currently are not supported.)
*/
- for (ts = 0; ts < tsdiff; ts++) {
- i = ts % 1024;
- store_sr_sample(samples, i, ss->lastsample);
-
- /*
- * If we have 1024 samples ready or we're at the
- * end of submitting the padding samples, submit
- * the packet to Sigrok. Since constant data is
- * sent, duplication of data for rates above 50MHz
- * is simple.
- */
- if ((i == 1023) || (ts == tsdiff - 1)) {
- logic.length = (i + 1) * logic.unitsize;
- for (j = 0; j < devc->samples_per_event; j++)
- sigma_session_send(sdi, &packet);
- }
+ ss = &devc->state;
+ ts = sigma_dram_cluster_ts(dram_cluster);
+ tsdiff = ts - ss->lastts;
+ if (tsdiff > 0) {
+ size_t count;
+ count = tsdiff * devc->samples_per_event;
+ (void)check_and_submit_sample(devc, ss->lastsample, count, FALSE);
}
+ ss->lastts = ts + EVENTS_PER_CLUSTER;
/*
- * Parse the samples in current cluster and prepare them
- * to be submitted to Sigrok. Cope with memory layouts that
- * vary with the samplerate.
+ * Grab sample data from the current cluster and prepare their
+ * submission to the session feed. Handle samplerate dependent
+ * memory layout of sample data. Accumulation of data chunks
+ * before submission is transparent to this code path, specific
+ * buffer depth is neither assumed nor required here.
*/
- send_ptr = &samples[0];
- send_count = 0;
sample = 0;
for (i = 0; i < events_in_cluster; i++) {
item16 = sigma_dram_cluster_data(dram_cluster, i);
if (devc->cur_samplerate == SR_MHZ(200)) {
sample = sigma_deinterlace_200mhz_data(item16, 0);
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_200mhz_data(item16, 1);
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_200mhz_data(item16, 2);
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_200mhz_data(item16, 3);
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
} else if (devc->cur_samplerate == SR_MHZ(100)) {
sample = sigma_deinterlace_100mhz_data(item16, 0);
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
sample = sigma_deinterlace_100mhz_data(item16, 1);
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
} else {
sample = item16;
- store_sr_sample(samples, send_count++, sample);
+ check_and_submit_sample(devc, sample, 1, triggered);
}
}
-
- /*
- * If a trigger position applies, then provide the datafeed with
- * the first part of data up to that position, then send the
- * trigger marker.
- */
- int trigger_offset = 0;
- if (triggered) {
- /*
- * Trigger is not always accurate to sample because of
- * pipeline delay. However, it always triggers before
- * the actual event. We therefore look at the next
- * samples to pinpoint the exact position of the trigger.
- */
- trigger_offset = get_trigger_offset(samples,
- ss->lastsample, &devc->trigger);
-
- if (trigger_offset > 0) {
- trig_count = trigger_offset * devc->samples_per_event;
- packet.type = SR_DF_LOGIC;
- logic.length = trig_count * logic.unitsize;
- sigma_session_send(sdi, &packet);
- send_ptr += trig_count * logic.unitsize;
- send_count -= trig_count;
- }
-
- /* Only send trigger if explicitly enabled. */
- if (devc->use_triggers) {
- packet.type = SR_DF_TRIGGER;
- sr_session_send(sdi, &packet);
- }
- }
-
- /*
- * Send the data after the trigger, or all of the received data
- * if no trigger position applies.
- */
- if (send_count) {
- packet.type = SR_DF_LOGIC;
- logic.length = send_count * logic.unitsize;
- logic.data = send_ptr;
- sigma_session_send(sdi, &packet);
- }
-
ss->lastsample = sample;
}
* For 50 MHz and below, events contain one sample for each channel,
* spread 20 ns apart.
*/
-static int decode_chunk_ts(struct sigma_dram_line *dram_line,
- uint16_t events_in_line,
- uint32_t trigger_event,
- struct sr_dev_inst *sdi)
+static int decode_chunk_ts(struct dev_context *devc,
+ struct sigma_dram_line *dram_line,
+ size_t events_in_line, size_t trigger_event)
{
struct sigma_dram_cluster *dram_cluster;
- struct dev_context *devc;
unsigned int clusters_in_line;
unsigned int events_in_cluster;
unsigned int i;
- uint32_t trigger_cluster, triggered;
+ uint32_t trigger_cluster;
- devc = sdi->priv;
clusters_in_line = events_in_line;
clusters_in_line += EVENTS_PER_CLUSTER - 1;
clusters_in_line /= EVENTS_PER_CLUSTER;
trigger_cluster = ~0;
- triggered = 0;
/* Check if trigger is in this chunk. */
- if (trigger_event < (64 * 7)) {
+ if (trigger_event < EVENTS_PER_ROW) {
if (devc->cur_samplerate <= SR_MHZ(50)) {
trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
trigger_event);
events_in_cluster = EVENTS_PER_CLUSTER;
}
- triggered = (i == trigger_cluster);
- sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
- triggered, sdi);
+ sigma_decode_dram_cluster(devc, dram_cluster,
+ events_in_cluster, i == trigger_cluster);
}
return SR_OK;
uint32_t dl_first_line, dl_line;
uint32_t dl_events_in_line;
uint32_t trg_line, trg_event;
+ int ret;
devc = sdi->priv;
- dl_events_in_line = 64 * 7;
-
- dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
- if (!dram_line)
- return FALSE;
+ dl_events_in_line = EVENTS_PER_ROW;
sr_info("Downloading sample data.");
devc->state.state = SIGMA_DOWNLOAD;
sigma_set_register(WRITE_MODE, WMR_FORCESTOP | WMR_SDRAMWRITEEN, devc);
do {
if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) {
- sr_err("sigma: failed while waiting for RMR_POSTTRIGGERED bit");
+ sr_err("failed while waiting for RMR_POSTTRIGGERED bit");
return FALSE;
}
} while (!(modestatus & RMR_POSTTRIGGERED));
/* Check if trigger has fired. */
if (sigma_read_register(READ_MODE, &modestatus, 1, devc) != 1) {
- sr_err("sigma: failed to read READ_MODE register");
+ sr_err("failed to read READ_MODE register");
return FALSE;
}
trg_line = ~0;
*
* When RMR_ROUND is set, the circular buffer in DRAM has wrapped
* around. Since the status of the very next line is uncertain in
- * that case, we skip it and start reading from the next line. The
- * circular buffer has 32K lines (0x8000).
+ * that case, we skip it and start reading from the next line.
*/
- dl_lines_total = (stoppos >> 9) + 1;
+ dl_first_line = 0;
+ dl_lines_total = (stoppos >> ROW_SHIFT) + 1;
if (modestatus & RMR_ROUND) {
dl_first_line = dl_lines_total + 1;
- dl_lines_total = 0x8000 - 2;
- } else {
- dl_first_line = 0;
+ dl_lines_total = ROW_COUNT - 2;
}
+ dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
+ if (!dram_line)
+ return FALSE;
+ ret = alloc_submit_buffer(sdi);
+ if (ret != SR_OK)
+ return FALSE;
+ ret = setup_submit_buffer(devc);
+ if (ret != SR_OK)
+ return FALSE;
dl_lines_done = 0;
while (dl_lines_total > dl_lines_done) {
/* We can download only up-to 32 DRAM lines in one go! */
dl_lines_curr = MIN(chunks_per_read, dl_lines_total - dl_lines_done);
dl_line = dl_first_line + dl_lines_done;
- dl_line %= 0x8000;
+ dl_line %= ROW_COUNT;
bufsz = sigma_read_dram(dl_line, dl_lines_curr,
(uint8_t *)dram_line, devc);
/* TODO: Check bufsz. For now, just avoid compiler warnings. */
if (dl_lines_done + i == trg_line)
trigger_event = trg_event;
- decode_chunk_ts(dram_line + i, dl_events_in_line,
- trigger_event, sdi);
+ decode_chunk_ts(devc, dram_line + i,
+ dl_events_in_line, trigger_event);
}
dl_lines_done += dl_lines_curr;
}
+ flush_submit_buffer(devc);
+ free_submit_buffer(devc);
g_free(dram_line);
std_session_send_df_end(sdi);