hantek-dso: hopefully handle endianness in voltage setting

[libsigrok.git] / sigrok.h.in

diff --git a/sigrok.h.in b/sigrok.h.in
index d40d72a15408aa41a73b86ef58f2883b6aa93619..18f9404a609c51666113a25cbeee0f186767a4a6 100644 (file)
--- a/sigrok.h.in
+++ b/sigrok.h.in
@@ -143,7 +143,8 @@ enum {
        SR_T_CHAR,
        SR_T_BOOL,
        SR_T_FLOAT,
-       SR_T_RATIONAL,
+       SR_T_RATIONAL_PERIOD,
+       SR_T_RATIONAL_VOLT,
 };
 
 struct sr_rational {
@@ -316,6 +317,15 @@ enum {
        /** Time base. */
        SR_HWCAP_TIMEBASE,
 
+       /** Filter. */
+       SR_HWCAP_FILTER,
+
+       /** Volts/div. */
+       SR_HWCAP_VDIV,
+
+       /** Coupling. */
+       SR_HWCAP_COUPLING,
+
        /*--- Special stuff -------------------------------------------------*/
 
        /* TODO: Better description. */
@@ -422,6 +432,12 @@ enum {
        SR_DI_TIMEBASES,
        /* Supported trigger sources */
        SR_DI_TRIGGER_SOURCES,
+       /* Supported filter targets */
+       SR_DI_FILTERS,
+       /* Valid volts/div values */
+       SR_DI_VDIVS,
+       /* Coupling options */
+       SR_DI_COUPLING,
 };
 
 /*