]> sigrok.org Git - libsigrok.git/blobdiff - sigrok.h.in
hantek-dso: hopefully handle endianness in voltage setting
[libsigrok.git] / sigrok.h.in
index 2b57bcfceeccc7574847d997582983f8d88022d9..18f9404a609c51666113a25cbeee0f186767a4a6 100644 (file)
@@ -142,6 +142,16 @@ enum {
        SR_T_UINT64,
        SR_T_CHAR,
        SR_T_BOOL,
+       SR_T_FLOAT,
+       SR_T_RATIONAL_PERIOD,
+       SR_T_RATIONAL_VOLT,
+};
+
+struct sr_rational {
+       /* numerator */
+       uint64_t p;
+       /* denominator */
+       uint64_t q;
 };
 
 /* sr_datafeed_packet.type values */
@@ -293,7 +303,28 @@ enum {
        SR_HWCAP_RLE,
 
        /** The device supports setting trigger slope. */
-       SR_HWCAP_TRIGGERSLOPE,
+       SR_HWCAP_TRIGGER_SLOPE,
+
+       /** Trigger source. */
+       SR_HWCAP_TRIGGER_SOURCE,
+
+       /** Horizontal trigger position */
+       SR_HWCAP_HORIZ_TRIGGERPOS,
+
+       /** Buffer size. */
+       SR_HWCAP_BUFFERSIZE,
+
+       /** Time base. */
+       SR_HWCAP_TIMEBASE,
+
+       /** Filter. */
+       SR_HWCAP_FILTER,
+
+       /** Volts/div. */
+       SR_HWCAP_VDIV,
+
+       /** Coupling. */
+       SR_HWCAP_COUPLING,
 
        /*--- Special stuff -------------------------------------------------*/
 
@@ -389,12 +420,24 @@ enum {
        SR_DI_PROBE_NAMES,
        /* Samplerates supported by this device, (struct sr_samplerates) */
        SR_DI_SAMPLERATES,
-       /* Types of trigger supported, out of "01crf" (char *) */
+       /* Types of logic trigger supported, out of "01crf" (char *) */
        SR_DI_TRIGGER_TYPES,
        /* The currently set samplerate in Hz (uint64_t) */
        SR_DI_CUR_SAMPLERATE,
        /* Supported patterns (in pattern generator mode) */
        SR_DI_PATTERNS,
+       /* Supported buffer sizes */
+       SR_DI_BUFFERSIZES,
+       /* Supported time bases */
+       SR_DI_TIMEBASES,
+       /* Supported trigger sources */
+       SR_DI_TRIGGER_SOURCES,
+       /* Supported filter targets */
+       SR_DI_FILTERS,
+       /* Valid volts/div values */
+       SR_DI_VDIVS,
+       /* Coupling options */
+       SR_DI_COUPLING,
 };
 
 /*