saleae-logic: fix timing on packets when triggering is used

[libsigrok.git] / hardware / saleae-logic / saleae-logic.c

diff --git a/hardware/saleae-logic/saleae-logic.c b/hardware/saleae-logic/saleae-logic.c
index c5a81e36e64cd30f14c250e3da43fa06f5112f56..a1ab755b149c2b0b6e479575e2b4ab1c468c1a0d 100644 (file)
--- a/hardware/saleae-logic/saleae-logic.c
+++ b/hardware/saleae-logic/saleae-logic.c
@@ -633,6 +633,7 @@ void receive_transfer(struct libusb_transfer *transfer)
                                /* Match on this trigger stage. */
                                fx2->trigger_buffer[fx2->trigger_stage] = cur_buf[i];
                                fx2->trigger_stage++;
+
                                if (fx2->trigger_stage == NUM_TRIGGER_STAGES || fx2->trigger_mask[fx2->trigger_stage] == 0) {
                                        /* Match on all trigger stages, we're done. */
                                        trigger_offset = i + 1;
@@ -642,7 +643,7 @@ void receive_transfer(struct libusb_transfer *transfer)
                                         * Tell the frontend we hit the trigger here.
                                         */
                                        packet.type = SR_DF_TRIGGER;
-                                       packet.timeoffset = (num_samples - fx2->trigger_stage) * fx2->period_ps;
+                                       packet.timeoffset = (num_samples + i) * fx2->period_ps;
                                        packet.duration = 0;
                                        packet.payload = NULL;
                                        sr_session_bus(fx2->session_data, &packet);
@@ -652,7 +653,7 @@ void receive_transfer(struct libusb_transfer *transfer)
                                         * skipping past them.
                                         */
                                        packet.type = SR_DF_LOGIC;
-                                       packet.timeoffset = (num_samples - fx2->trigger_stage) * fx2->period_ps;
+                                       packet.timeoffset = (num_samples + i) * fx2->period_ps;
                                        packet.duration = fx2->trigger_stage * fx2->period_ps;
                                        packet.payload = &logic;
                                        logic.length = fx2->trigger_stage;