#include <unistd.h>
#include <stdlib.h>
#include <string.h>
+#include <math.h>
#include <glib.h>
#include "libsigrok.h"
#include "libsigrok-internal.h"
static const uint64_t timebases[][2] = {
/* nanoseconds */
+ { 1, 1000000000 },
{ 2, 1000000000 },
{ 5, 1000000000 },
{ 10, 1000000000 },
{ 100, 1 },
{ 200, 1 },
{ 500, 1 },
- /* { 1000, 1 }, Confuses other code? */
+ { 1000, 1 },
};
static const uint64_t vdivs[][2] = {
#define RIGOL "Rigol Technologies"
#define AGILENT "Agilent Technologies"
+#define RIGOL_SHORT "Rigol"
+#define AGILENT_SHORT "Agilent"
static const struct rigol_ds_model supported_models[] = {
- {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
+ {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
+ {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
+ {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
+ {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
+ {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
+ {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
{RIGOL, "DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
{RIGOL, "DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
{RIGOL, "DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
return std_dev_clear(di, clear_helper);
}
-static int set_cfg(const struct sr_dev_inst *sdi, const char *format, ...)
-{
- va_list args;
- int ret;
-
- va_start(args, format);
- ret = sr_scpi_send_variadic(sdi->conn, format, args);
- va_end(args);
-
- if (ret != SR_OK)
- return SR_ERR;
-
- /* When setting a bunch of parameters in a row, the DS1052E scrambles
- * some of them unless there is at least 100ms delay in between. */
- sr_spew("delay %dms", 100);
- g_usleep(100000);
-
- return SR_OK;
-}
-
static int init(struct sr_context *sr_ctx)
{
return std_init(sr_ctx, di, LOG_PREFIX);
struct sr_scpi_dev_inst *scpi;
struct sr_scpi_hw_info *hw_info;
struct sr_probe *probe;
+ long n[3];
unsigned int i;
const struct rigol_ds_model *model = NULL;
- gchar *channel_name;
+ gchar *channel_name, *vendor, **version;
*devices = NULL;
}
}
+ if (!strcmp(hw_info->manufacturer, RIGOL))
+ vendor = RIGOL_SHORT;
+ else if (!strcmp(hw_info->manufacturer, AGILENT))
+ vendor = AGILENT_SHORT;
+ else
+ vendor = hw_info->manufacturer;
if (!model || !(sdi = sr_dev_inst_new(0, SR_ST_ACTIVE,
- hw_info->manufacturer, hw_info->model,
+ vendor, hw_info->model,
hw_info->firmware_version))) {
sr_scpi_hw_info_free(hw_info);
sr_scpi_close(scpi);
return SR_ERR_NA;
}
- sr_scpi_hw_info_free(hw_info);
sr_scpi_close(scpi);
sdi->conn = scpi;
devc->limit_frames = 0;
devc->model = model;
+ devc->protocol = model->protocol;
+
+ /* DS1000 models with firmware before 0.2.4 used the old
+ * legacy protocol. */
+ if (model->series == RIGOL_DS1000) {
+ version = g_strsplit(hw_info->firmware_version, ".", 0);
+ do {
+ if (!version[0] || !version[1] || !version[2])
+ break;
+ if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
+ break;
+ for (i = 0; i < 3; i++) {
+ if (sr_atol(version[i], &n[i]) != SR_OK)
+ break;
+ }
+ if (i != 3)
+ break;
+ if (n[0] != 0 || n[1] > 2)
+ break;
+ if (n[1] == 2 && n[2] > 3)
+ break;
+ sr_dbg("Found DS1000 firmware < 0.2.4, using old protocol.");
+ devc->protocol = PROTOCOL_LEGACY;
+ } while(0);
+ g_strfreev(version);
+ }
+
+ sr_scpi_hw_info_free(hw_info);
for (i = 0; i < model->analog_channels; i++) {
if (!(channel_name = g_strdup_printf("CH%d", i + 1)))
static int dev_close(struct sr_dev_inst *sdi)
{
struct sr_scpi_dev_inst *scpi;
+ struct dev_context *devc;
scpi = sdi->conn;
+ devc = sdi->priv;
+
+ if (devc->model->series != RIGOL_VS5000)
+ rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
if (scpi) {
if (sr_scpi_close(scpi) < 0)
int analog_probes = 0;
GSList *l;
- if (devc->model->protocol == PROTOCOL_LEGACY) {
- if (devc->model->series == RIGOL_VS5000)
- return VS5000_ANALOG_LIVE_WAVEFORM_SIZE;
- else
- return DS1000_ANALOG_LIVE_WAVEFORM_SIZE;
- } else {
+ switch (devc->model->series) {
+ case RIGOL_VS5000:
+ return VS5000_ANALOG_LIVE_WAVEFORM_SIZE;
+ case RIGOL_DS1000:
+ return DS1000_ANALOG_LIVE_WAVEFORM_SIZE;
+ default:
for (l = sdi->probes; l; l = l->next) {
probe = l->data;
if (probe->type == SR_PROBE_ANALOG && probe->enabled)
}
}
+static int digital_frame_size(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+
+ switch (devc->model->series) {
+ case RIGOL_VS5000:
+ return VS5000_DIGITAL_WAVEFORM_SIZE;
+ case RIGOL_DS1000:
+ return DS1000_DIGITAL_WAVEFORM_SIZE;
+ default:
+ return 0;
+ }
+}
+
static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
const struct sr_probe_group *probe_group)
{
struct dev_context *devc;
+ struct sr_probe *probe;
+ const char *tmp_str;
uint64_t samplerate;
+ int analog_channel = -1;
+ float smallest_diff = 0.0000000001;
+ int idx = -1;
+ unsigned i;
if (!sdi || !(devc = sdi->priv))
return SR_ERR_ARG;
return SR_ERR;
}
+ if (probe_group) {
+ probe = g_slist_nth_data(probe_group->probes, 0);
+ if (!probe)
+ return SR_ERR;
+ if (probe->type == SR_PROBE_ANALOG) {
+ if (probe->name[2] < '1' || probe->name[2] > '4')
+ return SR_ERR;
+ analog_channel = probe->name[2] - '1';
+ }
+ }
+
switch (id) {
case SR_CONF_NUM_TIMEBASE:
*data = g_variant_new_int32(devc->model->num_horizontal_divs);
break;
case SR_CONF_NUM_VDIV:
- *data = g_variant_new_int32(8);
+ *data = g_variant_new_int32(NUM_VDIV);
case SR_CONF_DATA_SOURCE:
if (devc->data_source == DATA_SOURCE_LIVE)
*data = g_variant_new_string("Live");
return SR_ERR_NA;
}
break;
+ case SR_CONF_TRIGGER_SOURCE:
+ if (!strcmp(devc->trigger_source, "ACL"))
+ tmp_str = "AC Line";
+ else if (!strcmp(devc->trigger_source, "CHAN1"))
+ tmp_str = "CH1";
+ else if (!strcmp(devc->trigger_source, "CHAN2"))
+ tmp_str = "CH2";
+ else if (!strcmp(devc->trigger_source, "CHAN3"))
+ tmp_str = "CH3";
+ else if (!strcmp(devc->trigger_source, "CHAN4"))
+ tmp_str = "CH4";
+ else
+ tmp_str = devc->trigger_source;
+ *data = g_variant_new_string(tmp_str);
+ break;
+ case SR_CONF_TIMEBASE:
+ for (i = 0; i < devc->num_timebases; i++) {
+ float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
+ float diff = fabs(devc->timebase - tb);
+ if (diff < smallest_diff) {
+ smallest_diff = diff;
+ idx = i;
+ }
+ }
+ if (idx < 0)
+ return SR_ERR_NA;
+ *data = g_variant_new("(tt)", devc->timebases[idx][0],
+ devc->timebases[idx][1]);
+ break;
+ case SR_CONF_VDIV:
+ if (analog_channel < 0)
+ return SR_ERR_NA;
+ for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
+ float vdiv = (float)vdivs[i][0] / vdivs[i][1];
+ float diff = fabs(devc->vdiv[analog_channel] - vdiv);
+ if (diff < smallest_diff) {
+ smallest_diff = diff;
+ idx = i;
+ }
+ }
+ if (idx < 0)
+ return SR_ERR_NA;
+ *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
+ break;
+ case SR_CONF_COUPLING:
+ if (analog_channel < 0)
+ return SR_ERR_NA;
+ *data = g_variant_new_string(devc->coupling[analog_channel]);
+ break;
default:
return SR_ERR_NA;
}
unsigned int i, j;
int ret;
const char *tmp_str;
+ char buffer[16];
if (!(devc = sdi->priv))
return SR_ERR_ARG;
return SR_ERR;
g_free(devc->trigger_slope);
devc->trigger_slope = g_strdup(tmp_u64 ? "POS" : "NEG");
- ret = set_cfg(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
+ ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
break;
case SR_CONF_HORIZ_TRIGGERPOS:
t_dbl = g_variant_get_double(data);
/* We have the trigger offset as a percentage of the frame, but
* need to express this in seconds. */
t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
- ret = set_cfg(sdi, ":TIM:OFFS %.6f", t_dbl);
+ g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
+ ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
break;
case SR_CONF_TIMEBASE:
g_variant_get(data, "(tt)", &p, &q);
for (i = 0; i < devc->num_timebases; i++) {
if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
devc->timebase = (float)p / q;
- ret = set_cfg(sdi, ":TIM:SCAL %.9f", devc->timebase);
+ g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
+ devc->timebase);
+ ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
break;
}
}
tmp_str = "CHAN4";
else
tmp_str = (char *)devc->trigger_source;
- ret = set_cfg(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
+ ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
break;
}
}
if (vdivs[j][0] != p || vdivs[j][1] != q)
continue;
devc->vdiv[i] = (float)p / q;
- return set_cfg(sdi, ":CHAN%d:SCAL %.3f", i + 1,
- devc->vdiv[i]);
+ g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
+ devc->vdiv[i]);
+ return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
+ buffer);
}
return SR_ERR_ARG;
}
if (!strcmp(tmp_str, coupling[j])) {
g_free(devc->coupling[i]);
devc->coupling[i] = g_strdup(coupling[j]);
- return set_cfg(sdi, ":CHAN%d:COUP %s", i + 1,
+ return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
devc->coupling[i]);
}
}
devc->data_source = DATA_SOURCE_LIVE;
else if (!strcmp(tmp_str, "Memory"))
devc->data_source = DATA_SOURCE_MEMORY;
- else if (devc->model->protocol == PROTOCOL_IEEE488_2
+ else if (devc->model->series >= RIGOL_DS1000Z
&& !strcmp(tmp_str, "Segmented"))
devc->data_source = DATA_SOURCE_SEGMENTED;
else
struct sr_scpi_dev_inst *scpi;
struct dev_context *devc;
struct sr_probe *probe;
+ struct sr_datafeed_packet packet;
GSList *l;
if (sdi->status != SR_ST_ACTIVE)
devc->enabled_analog_probes, probe);
if (probe->enabled != devc->analog_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (set_cfg(sdi, ":CHAN%d:DISP %s", probe->index + 1,
+ if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", probe->index + 1,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
devc->analog_channels[probe->index] = probe->enabled;
devc->enabled_digital_probes, probe);
/* Turn on LA module if currently off. */
if (!devc->la_enabled) {
- if (set_cfg(sdi, ":LA:DISP ON") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":LA:DISP ON") != SR_OK)
return SR_ERR;
devc->la_enabled = TRUE;
}
}
if (probe->enabled != devc->digital_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (set_cfg(sdi, ":DIG%d:TURN %s", probe->index,
+ if (rigol_ds_config_set(sdi, ":DIG%d:TURN %s", probe->index,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
devc->digital_channels[probe->index] = probe->enabled;
/* Turn off LA module if on and no digital probes selected. */
if (devc->la_enabled && !devc->enabled_digital_probes)
- if (set_cfg(sdi, ":LA:DISP OFF") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":LA:DISP OFF") != SR_OK)
return SR_ERR;
if (devc->data_source == DATA_SOURCE_LIVE) {
- if (set_cfg(sdi, ":RUN") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
return SR_ERR;
} else if (devc->data_source == DATA_SOURCE_MEMORY) {
if (devc->model->series != RIGOL_DS2000) {
devc->channel_entry = devc->enabled_digital_probes;
devc->analog_frame_size = analog_frame_size(sdi);
+ devc->digital_frame_size = digital_frame_size(sdi);
- if (devc->model->protocol == PROTOCOL_LEGACY) {
+ if (devc->model->series < RIGOL_DS1000Z) {
/* Fetch the first frame. */
if (rigol_ds_channel_start(sdi) != SR_OK)
return SR_ERR;
/* Apparently for the DS2000 the memory
* depth can only be set in Running state -
* this matches the behaviour of the UI. */
- if (set_cfg(sdi, ":RUN") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
return SR_ERR;
- if (set_cfg(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK)
+ if (rigol_ds_config_set(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK)
return SR_ERR;
- if (set_cfg(sdi, ":STOP") != SR_OK)
+ if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
return SR_ERR;
}
if (rigol_ds_capture_start(sdi) != SR_OK)
}
}
+ /* Start of first frame. */
+ packet.type = SR_DF_FRAME_BEGIN;
+ sr_session_send(cb_data, &packet);
+
return SR_OK;
}
projects / libsigrok.git / blobdiff