#include <unistd.h>
#include <stdlib.h>
#include <string.h>
+#include <math.h>
#include <glib.h>
#include "libsigrok.h"
#include "libsigrok-internal.h"
SR_CONF_TRIGGER_SLOPE,
SR_CONF_HORIZ_TRIGGERPOS,
SR_CONF_NUM_TIMEBASE,
+ SR_CONF_LIMIT_FRAMES,
+ SR_CONF_SAMPLERATE,
};
static const int32_t analog_hwcaps[] = {
static const uint64_t timebases[][2] = {
/* nanoseconds */
+ { 1, 1000000000 },
{ 2, 1000000000 },
{ 5, 1000000000 },
{ 10, 1000000000 },
{ 100, 1 },
{ 200, 1 },
{ 500, 1 },
- /* { 1000, 1 }, Confuses other code? */
+ { 1000, 1 },
};
static const uint64_t vdivs[][2] = {
"Segmented",
};
-/*
- * name, series, protocol flavor, min timebase, max timebase, min vdiv,
- * digital channels, number of horizontal divs
- */
+enum vendor {
+ RIGOL,
+ AGILENT,
+};
-#define RIGOL "Rigol Technologies"
-#define AGILENT "Agilent Technologies"
+enum series {
+ VS5000,
+ DS1000,
+ DS2000,
+ DS2000A,
+ DSO1000,
+};
+
+/* short name, full name */
+static const struct rigol_ds_vendor supported_vendors[] = {
+ [RIGOL] = {"Rigol", "Rigol Technologies"},
+ [AGILENT] = {"Agilent", "Rigol Technologies"},
+};
+#define VENDOR(x) &supported_vendors[x]
+/* vendor, series, protocol, max timebase, min vdiv, number of horizontal divs,
+ * live waveform samples, memory buffer samples */
+static const struct rigol_ds_series supported_series[] = {
+ [VS5000] = {VENDOR(RIGOL), "VS5000", PROTOCOL_V1, FORMAT_RAW,
+ {50, 1}, {2, 1000}, 14, 2048, 0},
+ [DS1000] = {VENDOR(RIGOL), "DS1000", PROTOCOL_V2, FORMAT_IEEE488_2,
+ {50, 1}, {2, 1000}, 12, 600, 1048576},
+ [DS2000] = {VENDOR(RIGOL), "DS2000", PROTOCOL_V3, FORMAT_IEEE488_2,
+ {500, 1}, {2, 1000}, 14, 1400, 14000},
+ [DS2000A] = {VENDOR(RIGOL), "DS2000A", PROTOCOL_V3, FORMAT_IEEE488_2,
+ {1000, 1}, {500, 1000000}, 14, 1400, 14000},
+ [DSO1000] = {VENDOR(AGILENT), "DSO1000", PROTOCOL_V3, FORMAT_IEEE488_2,
+ {50, 1}, {2, 1000}, 12, 600, 20480},
+};
+
+#define SERIES(x) &supported_series[x]
+/* series, model, min timebase, analog channels, digital */
static const struct rigol_ds_model supported_models[] = {
- {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2302", RIGOL_DS2000, PROTOCOL_IEEE488_2, {1, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2072A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2102A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2202A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "DS2302A", RIGOL_DS2000, PROTOCOL_IEEE488_2, {1, 1000000000}, {1000, 1}, {500, 1000000}, 2, false, 14},
- {RIGOL, "VS5022", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
- {RIGOL, "VS5022D", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
- {RIGOL, "VS5042", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
- {RIGOL, "VS5042D", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
- {RIGOL, "VS5062", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
- {RIGOL, "VS5062D", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
- {RIGOL, "VS5102", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
- {RIGOL, "VS5102D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
- {RIGOL, "VS5202", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 14},
- {RIGOL, "VS5202D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 14},
- {AGILENT, "DSO1002A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {AGILENT, "DSO1004A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12},
- {AGILENT, "DSO1012A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {AGILENT, "DSO1014A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12},
- {AGILENT, "DSO1022A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {AGILENT, "DSO1024A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 4, false, 12},
+ {SERIES(VS5000), "VS5022", {20, 1000000000}, 2, false},
+ {SERIES(VS5000), "VS5042", {10, 1000000000}, 2, false},
+ {SERIES(VS5000), "VS5062", {5, 1000000000}, 2, false},
+ {SERIES(VS5000), "VS5102", {2, 1000000000}, 2, false},
+ {SERIES(VS5000), "VS5202", {2, 1000000000}, 2, false},
+ {SERIES(VS5000), "VS5022D", {20, 1000000000}, 2, true},
+ {SERIES(VS5000), "VS5042D", {10, 1000000000}, 2, true},
+ {SERIES(VS5000), "VS5062D", {5, 1000000000}, 2, true},
+ {SERIES(VS5000), "VS5102D", {2, 1000000000}, 2, true},
+ {SERIES(VS5000), "VS5202D", {2, 1000000000}, 2, true},
+ {SERIES(DS1000), "DS1052E", {5, 1000000000}, 2, false},
+ {SERIES(DS1000), "DS1102E", {2, 1000000000}, 2, false},
+ {SERIES(DS1000), "DS1152E", {2, 1000000000}, 2, false},
+ {SERIES(DS1000), "DS1052D", {5, 1000000000}, 2, true},
+ {SERIES(DS1000), "DS1102D", {2, 1000000000}, 2, true},
+ {SERIES(DS1000), "DS1152D", {2, 1000000000}, 2, true},
+ {SERIES(DS2000), "DS2072", {5, 1000000000}, 2, false},
+ {SERIES(DS2000), "DS2102", {5, 1000000000}, 2, false},
+ {SERIES(DS2000), "DS2202", {2, 1000000000}, 2, false},
+ {SERIES(DS2000), "DS2302", {1, 1000000000}, 2, false},
+ {SERIES(DS2000A), "DS2072A", {5, 1000000000}, 2, false},
+ {SERIES(DS2000A), "DS2102A", {5, 1000000000}, 2, false},
+ {SERIES(DS2000A), "DS2202A", {2, 1000000000}, 2, false},
+ {SERIES(DS2000A), "DS2302A", {1, 1000000000}, 2, false},
+ {SERIES(DSO1000), "DSO1002A", {5, 1000000000}, 2, false},
+ {SERIES(DSO1000), "DSO1004A", {5, 1000000000}, 4, false},
+ {SERIES(DSO1000), "DSO1012A", {2, 1000000000}, 2, false},
+ {SERIES(DSO1000), "DSO1014A", {2, 1000000000}, 4, false},
+ {SERIES(DSO1000), "DSO1022A", {2, 1000000000}, 2, false},
+ {SERIES(DSO1000), "DSO1024A", {2, 1000000000}, 4, false},
};
SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
return std_dev_clear(di, clear_helper);
}
-static int set_cfg(const struct sr_dev_inst *sdi, const char *format, ...)
-{
- va_list args;
- int ret;
-
- va_start(args, format);
- ret = sr_scpi_send_variadic(sdi->conn, format, args);
- va_end(args);
-
- if (ret != SR_OK)
- return SR_ERR;
-
- /* When setting a bunch of parameters in a row, the DS1052E scrambles
- * some of them unless there is at least 100ms delay in between. */
- sr_spew("delay %dms", 100);
- g_usleep(100000);
-
- return SR_OK;
-}
-
static int init(struct sr_context *sr_ctx)
{
return std_init(sr_ctx, di, LOG_PREFIX);
struct sr_scpi_dev_inst *scpi;
struct sr_scpi_hw_info *hw_info;
struct sr_probe *probe;
+ long n[3];
unsigned int i;
const struct rigol_ds_model *model = NULL;
- gchar *channel_name;
+ gchar *channel_name, **version;
*devices = NULL;
}
for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
- if (!strcasecmp(hw_info->manufacturer, supported_models[i].vendor) &&
+ if (!strcasecmp(hw_info->manufacturer,
+ supported_models[i].series->vendor->full_name) &&
!strcmp(hw_info->model, supported_models[i].name)) {
model = &supported_models[i];
break;
}
if (!model || !(sdi = sr_dev_inst_new(0, SR_ST_ACTIVE,
- hw_info->manufacturer, hw_info->model,
+ model->series->vendor->name,
+ model->name,
hw_info->firmware_version))) {
sr_scpi_hw_info_free(hw_info);
sr_scpi_close(scpi);
return SR_ERR_NA;
}
- sr_scpi_hw_info_free(hw_info);
sr_scpi_close(scpi);
sdi->conn = scpi;
devc->limit_frames = 0;
devc->model = model;
+ devc->format = model->series->format;
+
+ /* DS1000 models with firmware before 0.2.4 used the old data format. */
+ if (model->series == SERIES(DS1000)) {
+ version = g_strsplit(hw_info->firmware_version, ".", 0);
+ do {
+ if (!version[0] || !version[1] || !version[2])
+ break;
+ if (version[0][0] == 0 || version[1][0] == 0 || version[2][0] == 0)
+ break;
+ for (i = 0; i < 3; i++) {
+ if (sr_atol(version[i], &n[i]) != SR_OK)
+ break;
+ }
+ if (i != 3)
+ break;
+ if (n[0] != 0 || n[1] > 2)
+ break;
+ if (n[1] == 2 && n[2] > 3)
+ break;
+ sr_dbg("Found DS1000 firmware < 0.2.4, using raw data format.");
+ devc->format = FORMAT_RAW;
+ } while(0);
+ g_strfreev(version);
+ }
+
+ sr_scpi_hw_info_free(hw_info);
for (i = 0; i < model->analog_channels; i++) {
if (!(channel_name = g_strdup_printf("CH%d", i + 1)))
for (i = 0; i < NUM_TIMEBASE; i++) {
if (!memcmp(&devc->model->min_timebase, &timebases[i], sizeof(uint64_t[2])))
devc->timebases = &timebases[i];
- if (!memcmp(&devc->model->max_timebase, &timebases[i], sizeof(uint64_t[2])))
+ if (!memcmp(&devc->model->series->max_timebase, &timebases[i], sizeof(uint64_t[2])))
devc->num_timebases = &timebases[i] - devc->timebases + 1;
}
for (i = 0; i < NUM_VDIV; i++)
- if (!memcmp(&devc->model->min_vdiv, &vdivs[i], sizeof(uint64_t[2])))
+ if (!memcmp(&devc->model->series->min_vdiv, &vdivs[i], sizeof(uint64_t[2])))
devc->vdivs = &vdivs[i];
if (!(devc->buffer = g_try_malloc(ACQ_BUFFER_SIZE)))
static int dev_close(struct sr_dev_inst *sdi)
{
struct sr_scpi_dev_inst *scpi;
+ struct dev_context *devc;
scpi = sdi->conn;
+ devc = sdi->priv;
+
+ if (devc->model->series->protocol >= PROTOCOL_V2)
+ rigol_ds_config_set(sdi, ":KEY:LOCK DISABLE");
if (scpi) {
if (sr_scpi_close(scpi) < 0)
return dev_clear();
}
+static int analog_frame_size(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+ struct sr_probe *probe;
+ int analog_probes = 0;
+ GSList *l;
+
+ for (l = sdi->probes; l; l = l->next) {
+ probe = l->data;
+ if (probe->type == SR_PROBE_ANALOG && probe->enabled)
+ analog_probes++;
+ }
+
+ switch (devc->data_source) {
+ case DATA_SOURCE_LIVE:
+ return devc->model->series->live_samples;
+ case DATA_SOURCE_MEMORY:
+ return devc->model->series->buffer_samples / analog_probes;
+ default:
+ return 0;
+ }
+}
+
+static int digital_frame_size(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+
+ switch (devc->data_source) {
+ case DATA_SOURCE_LIVE:
+ return devc->model->series->live_samples * 2;
+ case DATA_SOURCE_MEMORY:
+ return devc->model->series->buffer_samples * 2;
+ default:
+ return 0;
+ }
+}
+
static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
const struct sr_probe_group *probe_group)
{
struct dev_context *devc;
+ struct sr_probe *probe;
+ const char *tmp_str;
+ uint64_t samplerate;
+ int analog_channel = -1;
+ float smallest_diff = 0.0000000001;
+ int idx = -1;
+ unsigned i;
if (!sdi || !(devc = sdi->priv))
return SR_ERR_ARG;
/* If a probe group is specified, it must be a valid one. */
+ if (probe_group && !g_slist_find(sdi->probe_groups, probe_group)) {
+ sr_err("Invalid probe group specified.");
+ return SR_ERR;
+ }
+
if (probe_group) {
- if (probe_group != &devc->analog_groups[0]
- && probe_group != &devc->analog_groups[1]) {
- sr_err("Invalid probe group specified.");
+ probe = g_slist_nth_data(probe_group->probes, 0);
+ if (!probe)
return SR_ERR;
+ if (probe->type == SR_PROBE_ANALOG) {
+ if (probe->name[2] < '1' || probe->name[2] > '4')
+ return SR_ERR;
+ analog_channel = probe->name[2] - '1';
}
}
switch (id) {
case SR_CONF_NUM_TIMEBASE:
- *data = g_variant_new_int32(devc->model->num_horizontal_divs);
+ *data = g_variant_new_int32(devc->model->series->num_horizontal_divs);
break;
case SR_CONF_NUM_VDIV:
- *data = g_variant_new_int32(8);
+ *data = g_variant_new_int32(NUM_VDIV);
case SR_CONF_DATA_SOURCE:
if (devc->data_source == DATA_SOURCE_LIVE)
*data = g_variant_new_string("Live");
else
*data = g_variant_new_string("Segmented");
break;
+ case SR_CONF_SAMPLERATE:
+ if (devc->data_source == DATA_SOURCE_LIVE) {
+ samplerate = analog_frame_size(sdi) /
+ (devc->timebase * devc->model->series->num_horizontal_divs);
+ *data = g_variant_new_uint64(samplerate);
+ } else {
+ return SR_ERR_NA;
+ }
+ break;
+ case SR_CONF_TRIGGER_SOURCE:
+ if (!strcmp(devc->trigger_source, "ACL"))
+ tmp_str = "AC Line";
+ else if (!strcmp(devc->trigger_source, "CHAN1"))
+ tmp_str = "CH1";
+ else if (!strcmp(devc->trigger_source, "CHAN2"))
+ tmp_str = "CH2";
+ else if (!strcmp(devc->trigger_source, "CHAN3"))
+ tmp_str = "CH3";
+ else if (!strcmp(devc->trigger_source, "CHAN4"))
+ tmp_str = "CH4";
+ else
+ tmp_str = devc->trigger_source;
+ *data = g_variant_new_string(tmp_str);
+ break;
+ case SR_CONF_TIMEBASE:
+ for (i = 0; i < devc->num_timebases; i++) {
+ float tb = (float)devc->timebases[i][0] / devc->timebases[i][1];
+ float diff = fabs(devc->timebase - tb);
+ if (diff < smallest_diff) {
+ smallest_diff = diff;
+ idx = i;
+ }
+ }
+ if (idx < 0)
+ return SR_ERR_NA;
+ *data = g_variant_new("(tt)", devc->timebases[idx][0],
+ devc->timebases[idx][1]);
+ break;
+ case SR_CONF_VDIV:
+ if (analog_channel < 0)
+ return SR_ERR_NA;
+ for (i = 0; i < ARRAY_SIZE(vdivs); i++) {
+ float vdiv = (float)vdivs[i][0] / vdivs[i][1];
+ float diff = fabs(devc->vdiv[analog_channel] - vdiv);
+ if (diff < smallest_diff) {
+ smallest_diff = diff;
+ idx = i;
+ }
+ }
+ if (idx < 0)
+ return SR_ERR_NA;
+ *data = g_variant_new("(tt)", vdivs[idx][0], vdivs[idx][1]);
+ break;
+ case SR_CONF_COUPLING:
+ if (analog_channel < 0)
+ return SR_ERR_NA;
+ *data = g_variant_new_string(devc->coupling[analog_channel]);
+ break;
default:
return SR_ERR_NA;
}
unsigned int i, j;
int ret;
const char *tmp_str;
+ char buffer[16];
if (!(devc = sdi->priv))
return SR_ERR_ARG;
return SR_ERR_DEV_CLOSED;
/* If a probe group is specified, it must be a valid one. */
- if (probe_group) {
- if (probe_group != &devc->analog_groups[0]
- && probe_group != &devc->analog_groups[1]) {
- sr_err("Invalid probe group specified.");
- return SR_ERR;
- }
+ if (probe_group && !g_slist_find(sdi->probe_groups, probe_group)) {
+ sr_err("Invalid probe group specified.");
+ return SR_ERR;
}
ret = SR_OK;
return SR_ERR;
g_free(devc->trigger_slope);
devc->trigger_slope = g_strdup(tmp_u64 ? "POS" : "NEG");
- ret = set_cfg(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
+ ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SLOP %s", devc->trigger_slope);
break;
case SR_CONF_HORIZ_TRIGGERPOS:
t_dbl = g_variant_get_double(data);
/* We have the trigger offset as a percentage of the frame, but
* need to express this in seconds. */
t_dbl = -(devc->horiz_triggerpos - 0.5) * devc->timebase * devc->num_timebases;
- ret = set_cfg(sdi, ":TIM:OFFS %.6f", t_dbl);
+ g_ascii_formatd(buffer, sizeof(buffer), "%.6f", t_dbl);
+ ret = rigol_ds_config_set(sdi, ":TIM:OFFS %s", buffer);
break;
case SR_CONF_TIMEBASE:
g_variant_get(data, "(tt)", &p, &q);
for (i = 0; i < devc->num_timebases; i++) {
if (devc->timebases[i][0] == p && devc->timebases[i][1] == q) {
devc->timebase = (float)p / q;
- ret = set_cfg(sdi, ":TIM:SCAL %.9f", devc->timebase);
+ g_ascii_formatd(buffer, sizeof(buffer), "%.9f",
+ devc->timebase);
+ ret = rigol_ds_config_set(sdi, ":TIM:SCAL %s", buffer);
break;
}
}
tmp_str = "CHAN4";
else
tmp_str = (char *)devc->trigger_source;
- ret = set_cfg(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
+ ret = rigol_ds_config_set(sdi, ":TRIG:EDGE:SOUR %s", tmp_str);
break;
}
}
if (vdivs[j][0] != p || vdivs[j][1] != q)
continue;
devc->vdiv[i] = (float)p / q;
- return set_cfg(sdi, ":CHAN%d:SCAL %.3f", i + 1,
- devc->vdiv[i]);
+ g_ascii_formatd(buffer, sizeof(buffer), "%.3f",
+ devc->vdiv[i]);
+ return rigol_ds_config_set(sdi, ":CHAN%d:SCAL %s", i + 1,
+ buffer);
}
return SR_ERR_ARG;
}
if (!strcmp(tmp_str, coupling[j])) {
g_free(devc->coupling[i]);
devc->coupling[i] = g_strdup(coupling[j]);
- return set_cfg(sdi, ":CHAN%d:COUP %s", i + 1,
+ return rigol_ds_config_set(sdi, ":CHAN%d:COUP %s", i + 1,
devc->coupling[i]);
}
}
tmp_str = g_variant_get_string(data, NULL);
if (!strcmp(tmp_str, "Live"))
devc->data_source = DATA_SOURCE_LIVE;
- else if (!strcmp(tmp_str, "Memory"))
+ else if (devc->model->series->protocol >= PROTOCOL_V2
+ && !strcmp(tmp_str, "Memory"))
devc->data_source = DATA_SOURCE_MEMORY;
- else if (devc->model->protocol == PROTOCOL_IEEE488_2
+ else if (devc->model->series->protocol >= PROTOCOL_V3
&& !strcmp(tmp_str, "Segmented"))
devc->data_source = DATA_SOURCE_SEGMENTED;
else
}
switch (key) {
- break;
case SR_CONF_DEVICE_OPTIONS:
if (!probe_group) {
sr_err("No probe group specified.");
if (!devc)
/* Can't know this until we have the exact model. */
return SR_ERR_ARG;
+ if (devc->num_timebases <= 0)
+ return SR_ERR_NA;
g_variant_builder_init(&gvb, G_VARIANT_TYPE_ARRAY);
for (i = 0; i < devc->num_timebases; i++) {
rational[0] = g_variant_new_uint64(devc->timebases[i][0]);
if (!devc)
/* Can't know this until we have the exact model. */
return SR_ERR_ARG;
- /* This needs tweaking by series/model! */
- if (devc->model->series == RIGOL_DS2000)
- *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
- else
+ switch (devc->model->series->protocol) {
+ case PROTOCOL_V1:
+ *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 2);
+ break;
+ case PROTOCOL_V2:
*data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources) - 1);
+ break;
+ default:
+ *data = g_variant_new_strv(data_sources, ARRAY_SIZE(data_sources));
+ break;
+ }
break;
default:
return SR_ERR_NA;
struct sr_scpi_dev_inst *scpi;
struct dev_context *devc;
struct sr_probe *probe;
+ struct sr_datafeed_packet packet;
GSList *l;
if (sdi->status != SR_ST_ACTIVE)
scpi = sdi->conn;
devc = sdi->priv;
+ devc->num_frames = 0;
+
for (l = sdi->probes; l; l = l->next) {
probe = l->data;
sr_dbg("handling probe %s", probe->name);
devc->enabled_analog_probes, probe);
if (probe->enabled != devc->analog_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (set_cfg(sdi, ":CHAN%d:DISP %s", probe->index + 1,
+ if (rigol_ds_config_set(sdi, ":CHAN%d:DISP %s", probe->index + 1,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
+ devc->analog_channels[probe->index] = probe->enabled;
}
} else if (probe->type == SR_PROBE_LOGIC) {
- if (probe->enabled)
+ if (probe->enabled) {
devc->enabled_digital_probes = g_slist_append(
devc->enabled_digital_probes, probe);
+ /* Turn on LA module if currently off. */
+ if (!devc->la_enabled) {
+ if (rigol_ds_config_set(sdi, ":LA:DISP ON") != SR_OK)
+ return SR_ERR;
+ devc->la_enabled = TRUE;
+ }
+ }
if (probe->enabled != devc->digital_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
- if (set_cfg(sdi, ":DIG%d:TURN %s", probe->index,
+ if (rigol_ds_config_set(sdi, ":DIG%d:TURN %s", probe->index,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
+ devc->digital_channels[probe->index] = probe->enabled;
}
}
}
if (!devc->enabled_analog_probes && !devc->enabled_digital_probes)
return SR_ERR;
- if (devc->data_source == DATA_SOURCE_LIVE) {
- if (set_cfg(sdi, ":RUN") != SR_OK)
+ /* Turn off LA module if on and no digital probes selected. */
+ if (devc->la_enabled && !devc->enabled_digital_probes)
+ if (rigol_ds_config_set(sdi, ":LA:DISP OFF") != SR_OK)
return SR_ERR;
- } else if (devc->data_source == DATA_SOURCE_MEMORY) {
- if (devc->model->series != RIGOL_DS2000) {
- sr_err("Data source 'Memory' not supported for this device");
- return SR_ERR;
- }
- } else if (devc->data_source == DATA_SOURCE_SEGMENTED) {
+
+ /* Set memory mode. */
+ if (devc->data_source == DATA_SOURCE_SEGMENTED) {
sr_err("Data source 'Segmented' not yet supported");
return SR_ERR;
}
+ devc->analog_frame_size = analog_frame_size(sdi);
+ devc->digital_frame_size = digital_frame_size(sdi);
+
+ switch (devc->model->series->protocol) {
+ case PROTOCOL_V2:
+ if (rigol_ds_config_set(sdi, ":ACQ:MDEP LONG") != SR_OK)
+ return SR_ERR;
+ break;
+ case PROTOCOL_V3:
+ /* Apparently for the DS2000 the memory
+ * depth can only be set in Running state -
+ * this matches the behaviour of the UI. */
+ if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
+ return SR_ERR;
+ if (rigol_ds_config_set(sdi, ":ACQ:MDEP %d",
+ devc->analog_frame_size) != SR_OK)
+ return SR_ERR;
+ if (rigol_ds_config_set(sdi, ":STOP") != SR_OK)
+ return SR_ERR;
+ break;
+ default:
+ break;
+ }
+
+ if (devc->data_source == DATA_SOURCE_LIVE)
+ if (rigol_ds_config_set(sdi, ":RUN") != SR_OK)
+ return SR_ERR;
+
sr_scpi_source_add(scpi, G_IO_IN, 50, rigol_ds_receive, (void *)sdi);
/* Send header packet to the session bus. */
else
devc->channel_entry = devc->enabled_digital_probes;
- if (devc->model->protocol == PROTOCOL_LEGACY) {
- devc->analog_frame_size = (devc->model->series == RIGOL_VS5000 ?
- VS5000_ANALOG_LIVE_WAVEFORM_SIZE :
- DS1000_ANALOG_LIVE_WAVEFORM_SIZE);
- /* Fetch the first frame. */
- if (rigol_ds_channel_start(sdi) != SR_OK)
- return SR_ERR;
- } else {
- if (devc->enabled_analog_probes) {
- if (devc->data_source == DATA_SOURCE_MEMORY)
- {
- if (g_slist_length(devc->enabled_analog_probes) == 1)
- devc->analog_frame_size = DS2000_ANALOG_MEM_WAVEFORM_SIZE_1C;
- else
- devc->analog_frame_size = DS2000_ANALOG_MEM_WAVEFORM_SIZE_2C;
- /* Apparently for the DS2000 the memory
- * depth can only be set in Running state -
- * this matches the behaviour of the UI. */
- if (set_cfg(sdi, ":RUN") != SR_OK)
- return SR_ERR;
- if (set_cfg(sdi, "ACQ:MDEP %d", devc->analog_frame_size) != SR_OK)
- return SR_ERR;
- if (set_cfg(sdi, ":STOP") != SR_OK)
- return SR_ERR;
- } else {
- if (devc->model->series == AGILENT_DSO1000)
- devc->analog_frame_size = DSO1000_ANALOG_LIVE_WAVEFORM_SIZE;
- else
- devc->analog_frame_size = DS2000_ANALOG_LIVE_WAVEFORM_SIZE;
- }
- if (rigol_ds_capture_start(sdi) != SR_OK)
- return SR_ERR;
- }
- }
+ if (rigol_ds_capture_start(sdi) != SR_OK)
+ return SR_ERR;
+
+ /* Start of first frame. */
+ packet.type = SR_DF_FRAME_BEGIN;
+ sr_session_send(cb_data, &packet);
return SR_OK;
}
{
struct dev_context *devc;
struct sr_scpi_dev_inst *scpi;
+ struct sr_datafeed_packet packet;
(void)cb_data;
return SR_ERR;
}
+ /* End of last frame. */
+ packet.type = SR_DF_END;
+ sr_session_send(sdi, &packet);
+
g_slist_free(devc->enabled_analog_probes);
g_slist_free(devc->enabled_digital_probes);
devc->enabled_analog_probes = NULL;
projects / libsigrok.git / blobdiff