rigol-ds: Use correct live waveform size for Agilent DSO1000 series.

[libsigrok.git] / hardware / rigol-ds / api.c

diff --git a/hardware/rigol-ds/api.c b/hardware/rigol-ds/api.c
index aafbb6b841eb5f788da2b628c0c6e8e600d62917..584a4fd65f22d0e2452cf44cad02860257ab2a89 100644 (file)
--- a/hardware/rigol-ds/api.c
+++ b/hardware/rigol-ds/api.c
@@ -154,26 +154,31 @@ static const char *data_sources[] = {
  * name, series, protocol flavor, min timebase, max timebase, min vdiv,
  * digital channels, number of horizontal divs
  */
+
+#define RIGOL "Rigol Technologies"
+#define AGILENT "Agilent Technologies"
+
 static const struct rigol_ds_model supported_models[] = {
-       {"DS1052E", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, false, 12},
-       {"DS1102E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 12},
-       {"DS1152E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 12},
-       {"DS1052D", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, true, 12},
-       {"DS1102D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 12},
-       {"DS1152D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 12},
-       {"DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, false, 14},
-       {"DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, false, 14},
-       {"DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, false, 14},
-       {"VS5022", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, false, 14},
-       {"VS5022D", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, true, 14},
-       {"VS5042", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, false, 14},
-       {"VS5042D", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, true, 14},
-       {"VS5062", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, false, 14},
-       {"VS5062D", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, true, 14},
-       {"VS5102", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 14},
-       {"VS5102D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 14},
-       {"VS5202", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 14},
-       {"VS5202D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 14},
+       {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, false, 12},
+       {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 12},
+       {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 12},
+       {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, true, 12},
+       {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 12},
+       {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 12},
+       {RIGOL, "DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, false, 14},
+       {RIGOL, "DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, false, 14},
+       {RIGOL, "DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, false, 14},
+       {RIGOL, "VS5022", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, false, 14},
+       {RIGOL, "VS5022D", RIGOL_VS5000, PROTOCOL_LEGACY, {20, 1000000000}, {50, 1}, {2, 1000}, true, 14},
+       {RIGOL, "VS5042", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, false, 14},
+       {RIGOL, "VS5042D", RIGOL_VS5000, PROTOCOL_LEGACY, {10, 1000000000}, {50, 1}, {2, 1000}, true, 14},
+       {RIGOL, "VS5062", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, false, 14},
+       {RIGOL, "VS5062D", RIGOL_VS5000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, true, 14},
+       {RIGOL, "VS5102", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 14},
+       {RIGOL, "VS5102D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 14},
+       {RIGOL, "VS5202", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, false, 14},
+       {RIGOL, "VS5202D", RIGOL_VS5000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, true, 14},
+       {AGILENT, "DSO1014A", AGILENT_DSO1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, false, 12},
 };
 
 SR_PRIV struct sr_dev_driver rigol_ds_driver_info;
@@ -266,6 +271,7 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev
        }
 
        if (sr_scpi_open(scpi) != SR_OK) {
+               sr_info("Couldn't open SCPI device.");
                sr_scpi_free(scpi);
                return SR_ERR;
        };
@@ -277,15 +283,9 @@ static int probe_port(const char *resource, const char *serialcomm, GSList **dev
                return SR_ERR;
        }
 
-       if (strcasecmp(hw_info->manufacturer, "Rigol Technologies")) {
-               sr_scpi_hw_info_free(hw_info);
-               sr_scpi_close(scpi);
-               sr_scpi_free(scpi);
-               return SR_ERR_NA;
-       }
-
        for (i = 0; i < ARRAY_SIZE(supported_models); i++) {
-               if (!strcmp(hw_info->model, supported_models[i].name)) {
+               if (!strcasecmp(hw_info->manufacturer, supported_models[i].vendor) &&
+                               !strcmp(hw_info->model, supported_models[i].name)) {
                        model = &supported_models[i];
                        break;
                }
@@ -864,8 +864,12 @@ static int dev_acquisition_start(const struct sr_dev_inst *sdi, void *cb_data)
                                        return SR_ERR;
                                if (set_cfg(sdi, ":STOP") != SR_OK)
                                        return SR_ERR;
-                       } else
-                               devc->analog_frame_size = DS2000_ANALOG_LIVE_WAVEFORM_SIZE;
+                       } else {
+                               if (devc->model->series == AGILENT_DSO1000)
+                                       devc->analog_frame_size = DSO1000_ANALOG_LIVE_WAVEFORM_SIZE;
+                               else
+                                       devc->analog_frame_size = DS2000_ANALOG_LIVE_WAVEFORM_SIZE;
+                       }
                        devc->channel = devc->enabled_analog_probes->data;
                        if (rigol_ds_capture_start(sdi) != SR_OK)
                                return SR_ERR;