#define AGILENT "Agilent Technologies"
static const struct rigol_ds_model supported_models[] = {
- {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
- {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_LEGACY, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
- {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_LEGACY, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
+ {RIGOL, "DS1052E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
+ {RIGOL, "DS1102E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
+ {RIGOL, "DS1152E", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, false, 12},
+ {RIGOL, "DS1052D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {5, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
+ {RIGOL, "DS1102D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
+ {RIGOL, "DS1152D", RIGOL_DS1000, PROTOCOL_IEEE488_2, {2, 1000000000}, {50, 1}, {2, 1000}, 2, true, 12},
{RIGOL, "DS2072", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
{RIGOL, "DS2102", RIGOL_DS2000, PROTOCOL_IEEE488_2, {5, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
{RIGOL, "DS2202", RIGOL_DS2000, PROTOCOL_IEEE488_2, {2, 1000000000}, {500, 1}, {500, 1000000}, 2, false, 14},
int analog_probes = 0;
GSList *l;
- if (devc->model->protocol == PROTOCOL_LEGACY) {
- if (devc->model->series == RIGOL_VS5000)
- return VS5000_ANALOG_LIVE_WAVEFORM_SIZE;
- else
- return DS1000_ANALOG_LIVE_WAVEFORM_SIZE;
- } else {
+ switch (devc->model->series) {
+ case RIGOL_VS5000:
+ return VS5000_ANALOG_LIVE_WAVEFORM_SIZE;
+ case RIGOL_DS1000:
+ return DS1000_ANALOG_LIVE_WAVEFORM_SIZE;
+ default:
for (l = sdi->probes; l; l = l->next) {
probe = l->data;
if (probe->type == SR_PROBE_ANALOG && probe->enabled)
}
}
+static int digital_frame_size(const struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+
+ switch (devc->model->series) {
+ case RIGOL_VS5000:
+ return VS5000_DIGITAL_WAVEFORM_SIZE;
+ case RIGOL_DS1000:
+ return DS1000_DIGITAL_WAVEFORM_SIZE;
+ default:
+ return 0;
+ }
+}
+
static int config_get(int id, GVariant **data, const struct sr_dev_inst *sdi,
const struct sr_probe_group *probe_group)
{
struct dev_context *devc;
+ uint64_t samplerate;
if (!sdi || !(devc = sdi->priv))
return SR_ERR_ARG;
/* If a probe group is specified, it must be a valid one. */
- if (probe_group && !g_slist_find(sdi->probe_groups, probe_group))
- {
+ if (probe_group && !g_slist_find(sdi->probe_groups, probe_group)) {
sr_err("Invalid probe group specified.");
return SR_ERR;
}
break;
case SR_CONF_SAMPLERATE:
if (devc->data_source == DATA_SOURCE_LIVE) {
- uint64_t samplerate = analog_frame_size(sdi) /
+ samplerate = analog_frame_size(sdi) /
(devc->timebase * devc->model->num_horizontal_divs);
*data = g_variant_new_uint64(samplerate);
- }
- else
+ } else {
return SR_ERR_NA;
+ }
break;
default:
return SR_ERR_NA;
return SR_ERR_DEV_CLOSED;
/* If a probe group is specified, it must be a valid one. */
- if (probe_group && !g_slist_find(sdi->probe_groups, probe_group))
- {
+ if (probe_group && !g_slist_find(sdi->probe_groups, probe_group)) {
sr_err("Invalid probe group specified.");
return SR_ERR;
}
devc->data_source = DATA_SOURCE_LIVE;
else if (!strcmp(tmp_str, "Memory"))
devc->data_source = DATA_SOURCE_MEMORY;
- else if (devc->model->protocol == PROTOCOL_IEEE488_2
+ else if (devc->model->series >= RIGOL_DS1000Z
&& !strcmp(tmp_str, "Segmented"))
devc->data_source = DATA_SOURCE_SEGMENTED;
else
scpi = sdi->conn;
devc = sdi->priv;
+ devc->num_frames = 0;
+
for (l = sdi->probes; l; l = l->next) {
probe = l->data;
sr_dbg("handling probe %s", probe->name);
if (set_cfg(sdi, ":CHAN%d:DISP %s", probe->index + 1,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
+ devc->analog_channels[probe->index] = probe->enabled;
}
} else if (probe->type == SR_PROBE_LOGIC) {
- if (probe->enabled)
+ if (probe->enabled) {
devc->enabled_digital_probes = g_slist_append(
devc->enabled_digital_probes, probe);
+ /* Turn on LA module if currently off. */
+ if (!devc->la_enabled) {
+ if (set_cfg(sdi, ":LA:DISP ON") != SR_OK)
+ return SR_ERR;
+ devc->la_enabled = TRUE;
+ }
+ }
if (probe->enabled != devc->digital_channels[probe->index]) {
/* Enabled channel is currently disabled, or vice versa. */
if (set_cfg(sdi, ":DIG%d:TURN %s", probe->index,
probe->enabled ? "ON" : "OFF") != SR_OK)
return SR_ERR;
+ devc->digital_channels[probe->index] = probe->enabled;
}
}
}
if (!devc->enabled_analog_probes && !devc->enabled_digital_probes)
return SR_ERR;
+ /* Turn off LA module if on and no digital probes selected. */
+ if (devc->la_enabled && !devc->enabled_digital_probes)
+ if (set_cfg(sdi, ":LA:DISP OFF") != SR_OK)
+ return SR_ERR;
+
if (devc->data_source == DATA_SOURCE_LIVE) {
if (set_cfg(sdi, ":RUN") != SR_OK)
return SR_ERR;
devc->channel_entry = devc->enabled_digital_probes;
devc->analog_frame_size = analog_frame_size(sdi);
+ devc->digital_frame_size = digital_frame_size(sdi);
- if (devc->model->protocol == PROTOCOL_LEGACY) {
+ if (devc->model->series < RIGOL_DS1000Z) {
/* Fetch the first frame. */
if (rigol_ds_channel_start(sdi) != SR_OK)
return SR_ERR;
} else {
if (devc->enabled_analog_probes) {
- if (devc->data_source == DATA_SOURCE_MEMORY)
- {
+ if (devc->data_source == DATA_SOURCE_MEMORY) {
/* Apparently for the DS2000 the memory
* depth can only be set in Running state -
* this matches the behaviour of the UI. */
{
struct dev_context *devc;
struct sr_scpi_dev_inst *scpi;
+ struct sr_datafeed_packet packet;
(void)cb_data;
return SR_ERR;
}
+ /* End of last frame. */
+ packet.type = SR_DF_END;
+ sr_session_send(sdi, &packet);
+
g_slist_free(devc->enabled_analog_probes);
g_slist_free(devc->enabled_digital_probes);
devc->enabled_analog_probes = NULL;
projects / libsigrok.git / blobdiff