* This file is part of the sigrok project.
*
* Copyright (C) 2011 Daniel Ribeiro <drwyrm@gmail.com>
+ * Copyright (C) 2012 Renato Caldas <rmsc@fe.up.pt>
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
#ifndef SIGROK_LINK_MSO19_H
#define SIGROK_LINK_MSO19_H
+/* Structure for the pattern generator state */
+struct mso_patgen {
+ /* Pattern generator clock config */
+ uint16_t clock;
+ /* Buffer start address */
+ uint16_t start;
+ /* Buffer end address */
+ uint16_t end;
+ /* Pattern generator config */
+ uint8_t config;
+ /* Samples buffer */
+ uint8_t buffer[1024];
+ /* Input/output configuration for the samples buffer (?)*/
+ uint8_t io[1024];
+ /* Number of loops for the pattern generator */
+ uint8_t loops;
+ /* Bit enable mask for the I/O lines */
+ uint8_t mask;
+};
+
+/* Data structure for the protocol trigger state */
+struct mso_prototrig {
+ /* Word match buffer */
+ uint8_t word[4];
+ /* Masks for the wordmatch buffer */
+ uint8_t mask[4];
+ /* SPI mode 0, 1, 2, 3. Set to 0 for I2C */
+ uint8_t spimode;
+};
+
/* our private per-instance data */
struct mso {
/* info */
uint16_t dac_offset;
uint16_t offset_range;
/* register cache */
- uint8_t ctlbase;
- uint8_t slowmode;
+ uint8_t ctlbase1;
+ uint8_t ctlbase2;
/* state */
uint8_t la_threshold;
uint64_t cur_rate;
uint8_t dso_probe_attn;
uint8_t trigger_chan;
uint8_t trigger_slope;
- uint8_t trigger_spimode;
uint8_t trigger_outsrc;
uint8_t trigger_state;
uint8_t la_trigger;
uint8_t la_trigger_mask;
double dso_trigger_voltage;
uint16_t dso_trigger_width;
+ struct mso_prototrig protocol_trigger;
gpointer session_id;
uint16_t buffer_n;
char buffer[4096];
const char mso_head[] = { 0x40, 0x4c, 0x44, 0x53, 0x7e };
const char mso_foot[] = { 0x7e };
-/* registers */
+/* bank agnostic registers */
+#define REG_CTL2 15
+
+/* bank 0 registers */
#define REG_BUFFER 1
#define REG_TRIGGER 2
#define REG_CLKRATE1 9
#define REG_CLKRATE2 10
#define REG_DAC1 12
#define REG_DAC2 13
-#define REG_CTL 14
+/* possibly bank agnostic: */
+#define REG_CTL1 14
+
+/* bank 2 registers (SPI/I2C protocol trigger) */
+#define REG_PT_WORD(x) (x)
+#define REG_PT_MASK(x) (x+4)
+#define REG_PT_SPIMODE 8
+
+/* bits - REG_CTL1 */
+#define BIT_CTL1_RESETFSM (1 << 0)
+#define BIT_CTL1_ARM (1 << 1)
+#define BIT_CTL1_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
+#define BIT_CTL1_RESETADC (1 << 6)
+#define BIT_CTL1_LED (1 << 7)
-/* bits */
-#define BIT_CTL_RESETFSM (1 << 0)
-#define BIT_CTL_ARM (1 << 1)
-#define BIT_CTL_ADC_UNKNOWN4 (1 << 4) /* adc enable? */
-#define BIT_CTL_RESETADC (1 << 6)
-#define BIT_CTL_LED (1 << 7)
+/* bits - REG_CTL2 */
+#define BITS_CTL2_BANK(x) (x & 0x3)
+#define BIT_CTL2_SLOWMODE (1 << 5)
struct rate_map {
uint32_t rate;
};
/* FIXME: Determine corresponding voltages */
-uint16_t la_threshold_map[] = {
+static uint16_t la_threshold_map[] = {
0x8600,
0x8770,
0x88ff,