SR_CONF_TRIGGER_TYPE,
SR_CONF_CAPTURE_RATIO,
SR_CONF_LIMIT_MSEC,
- SR_CONF_LIMIT_SAMPLES,
};
static const char *sigma_firmware_files[] = {
sr_info("Found ASIX SIGMA - Serial: %s", serial_txt);
- devc->cur_samplerate = 0;
+ devc->cur_samplerate = samplerates[0];
devc->period_ps = 0;
devc->limit_msec = 0;
devc->cur_firmware = -1;
if (samplerate <= SR_MHZ(50)) {
ret = upload_firmware(0, devc);
devc->num_channels = 16;
- }
- if (samplerate == SR_MHZ(100)) {
+ } else if (samplerate == SR_MHZ(100)) {
ret = upload_firmware(1, devc);
devc->num_channels = 8;
- }
- else if (samplerate == SR_MHZ(200)) {
+ } else if (samplerate == SR_MHZ(200)) {
ret = upload_firmware(2, devc);
devc->num_channels = 4;
}
- devc->cur_samplerate = samplerate;
- devc->period_ps = 1000000000000ULL / samplerate;
- devc->samples_per_event = 16 / devc->num_channels;
- devc->state.state = SIGMA_IDLE;
+ if (ret == SR_OK) {
+ devc->cur_samplerate = samplerate;
+ devc->period_ps = 1000000000000ULL / samplerate;
+ devc->samples_per_event = 16 / devc->num_channels;
+ devc->state.state = SIGMA_IDLE;
+ }
return ret;
}
(void)cg;
+ if (!sdi)
+ return SR_ERR;
+ devc = sdi->priv;
+
switch (id) {
case SR_CONF_SAMPLERATE:
- if (sdi) {
- devc = sdi->priv;
- *data = g_variant_new_uint64(devc->cur_samplerate);
- } else
- return SR_ERR;
+ *data = g_variant_new_uint64(devc->cur_samplerate);
+ break;
+ case SR_CONF_LIMIT_MSEC:
+ *data = g_variant_new_uint64(devc->limit_msec);
+ break;
+ case SR_CONF_CAPTURE_RATIO:
+ *data = g_variant_new_uint64(devc->capture_ratio);
break;
default:
return SR_ERR_NA;
const struct sr_channel_group *cg)
{
struct dev_context *devc;
- uint64_t num_samples;
- int ret = 0;
+ uint64_t tmp;
+ int ret;
(void)cg;
devc = sdi->priv;
+ ret = SR_OK;
switch (id) {
case SR_CONF_SAMPLERATE:
ret = set_samplerate(sdi, g_variant_get_uint64(data));
break;
case SR_CONF_LIMIT_MSEC:
- devc->limit_msec = g_variant_get_uint64(data);
- if (devc->limit_msec > 0)
- ret = SR_OK;
+ tmp = g_variant_get_uint64(data);
+ if (tmp > 0)
+ devc->limit_msec = g_variant_get_uint64(data);
else
ret = SR_ERR;
break;
case SR_CONF_LIMIT_SAMPLES:
- num_samples = g_variant_get_uint64(data);
- devc->limit_msec = num_samples * 1000 / devc->cur_samplerate;
+ tmp = g_variant_get_uint64(data);
+ devc->limit_msec = tmp * 1000 / devc->cur_samplerate;
break;
case SR_CONF_CAPTURE_RATIO:
- devc->capture_ratio = g_variant_get_uint64(data);
- if (devc->capture_ratio < 0 || devc->capture_ratio > 100)
- ret = SR_ERR;
+ tmp = g_variant_get_uint64(data);
+ if (tmp <= 100)
+ devc->capture_ratio = tmp;
else
- ret = SR_OK;
+ ret = SR_ERR;
break;
default:
ret = SR_ERR_NA;
static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
unsigned int events_in_cluster,
+ unsigned int triggered,
struct sr_dev_inst *sdi)
{
struct dev_context *devc = sdi->priv;
uint8_t samples[2048];
unsigned int i;
- int triggerts = -1;
-
ts = sigma_dram_cluster_ts(dram_cluster);
tsdiff = ts - ss->lastts;
ss->lastts = ts;
/* Send data up to trigger point (if triggered). */
int trigger_offset = 0;
- if ((int)i == triggerts) {
+ if (triggered) {
/*
* Trigger is not always accurate to sample because of
* pipeline delay. However, it always triggers before
* For 50 MHz and below, events contain one sample for each channel,
* spread 20 ns apart.
*/
-static int decode_chunk_ts(struct sigma_dram_line *dram_line, int triggerpos,
- uint16_t events_in_line, void *cb_data)
+static int decode_chunk_ts(struct sigma_dram_line *dram_line,
+ uint16_t events_in_line,
+ uint32_t trigger_event,
+ void *cb_data)
{
struct sigma_dram_cluster *dram_cluster;
struct sr_dev_inst *sdi = cb_data;
(events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
unsigned int events_in_cluster;
unsigned int i;
- int triggerts = -1;
+ uint32_t trigger_cluster = ~0, triggered = 0;
/* Check if trigger is in this chunk. */
- if (triggerpos != -1) {
- if (devc->cur_samplerate <= SR_MHZ(50))
- triggerpos -= EVENTS_PER_CLUSTER - 1;
-
- if (triggerpos < 0)
- triggerpos = 0;
+ if (trigger_event < (64 * 7)) {
+ if (devc->cur_samplerate <= SR_MHZ(50)) {
+ trigger_event -= MIN(EVENTS_PER_CLUSTER - 1,
+ trigger_event);
+ }
/* Find in which cluster the trigger occured. */
- triggerts = triggerpos / EVENTS_PER_CLUSTER;
+ trigger_cluster = trigger_event / EVENTS_PER_CLUSTER;
}
/* For each full DRAM cluster. */
events_in_cluster = EVENTS_PER_CLUSTER;
}
- sigma_decode_dram_cluster(dram_cluster, events_in_cluster, sdi);
+ triggered = (i == trigger_cluster);
+ sigma_decode_dram_cluster(dram_cluster, events_in_cluster,
+ triggered, sdi);
}
return SR_OK;
uint32_t i;
uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
uint32_t dl_events_in_line = 64 * 7;
- uint32_t trg_line = ~0;
+ uint32_t trg_line = ~0, trg_event = ~0;
dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
if (!dram_line)
/* Check if trigger has fired. */
modestatus = sigma_get_register(READ_MODE, devc);
- if (modestatus & 0x20)
+ if (modestatus & 0x20) {
trg_line = triggerpos >> 9;
+ trg_event = triggerpos & 0x1ff;
+ }
/*
* Determine how many 1024b "DRAM lines" do we need to read from the
}
for (i = 0; i < dl_lines_curr; i++) {
- int trigger_line = -1;
+ uint32_t trigger_event = ~0;
/* The last "DRAM line" can be only partially full. */
if (dl_lines_done + i == dl_lines_total - 1)
dl_events_in_line = stoppos & 0x1ff;
/* Test if the trigger happened on this line. */
if (dl_lines_done + i == trg_line)
- trigger_line = trg_line;
+ trigger_event = trg_event;
- decode_chunk_ts(dram_line + i, trigger_line,
- dl_events_in_line, sdi);
+ decode_chunk_ts(dram_line + i, dl_events_in_line,
+ trigger_event, sdi);
}
dl_lines_done += dl_lines_curr;
projects / libsigrok.git / blobdiff