SR_CONF_LIMIT_SAMPLES,
};
-/* Initialize the logic analyzer mode. */
-static uint8_t logic_mode_start[] = {
- 0x00, 0x40, 0x0f, 0x25, 0x35, 0x40,
- 0x2a, 0x3a, 0x40, 0x03, 0x20, 0x38,
-};
-
static const char *sigma_firmware_files[] = {
/* 50 MHz, supports 8 bit fractions */
FIRMWARE_DIR "/asix-sigma-50.fw",
return SR_OK;
}
-/*
- * Read the firmware from a file and transform it into a series of bitbang
- * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
- * by the caller of this function.
- */
-static int sigma_fw_2_bitbang(const char *filename,
- uint8_t **bb_cmd, gsize *bb_cmd_size)
-{
- GMappedFile *file;
- GError *error;
- gsize i, file_size, bb_size;
- gchar *firmware;
- uint8_t *bb_stream, *bbs;
- uint32_t imm;
- int bit, v;
- int ret = SR_OK;
-
- /*
- * Map the file and make the mapped buffer writable.
- * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
- * will be modified. It will not be modified until someone uses
- * g_file_set_contents() on it.
- */
- error = NULL;
- file = g_mapped_file_new(filename, TRUE, &error);
- g_assert_no_error(error);
-
- file_size = g_mapped_file_get_length(file);
- firmware = g_mapped_file_get_contents(file);
- g_assert(firmware);
-
- /* Weird magic transformation below, I have no idea what it does. */
- imm = 0x3f6df2ab;
- for (i = 0; i < file_size; i++) {
- imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
- firmware[i] ^= imm & 0xff;
- }
-
- /*
- * Now that the firmware is "transformed", we will transcribe the
- * firmware blob into a sequence of toggles of the Dx wires. This
- * sequence will be fed directly into the Sigma, which must be in
- * the FPGA bitbang programming mode.
- */
-
- /* Each bit of firmware is transcribed as two toggles of Dx wires. */
- bb_size = file_size * 8 * 2;
- bb_stream = (uint8_t *)g_try_malloc(bb_size);
- if (!bb_stream) {
- sr_err("%s: Failed to allocate bitbang stream", __func__);
- ret = SR_ERR_MALLOC;
- goto exit;
- }
-
- bbs = bb_stream;
- for (i = 0; i < file_size; i++) {
- for (bit = 7; bit >= 0; bit--) {
- v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
- *bbs++ = v | 0x01;
- *bbs++ = v;
- }
- }
-
- /* The transformation completed successfully, return the result. */
- *bb_cmd = bb_stream;
- *bb_cmd_size = bb_size;
-
-exit:
- g_mapped_file_unref(file);
- return ret;
-}
-
static void clear_helper(void *priv)
{
struct dev_context *devc;
return SR_ERR_TIMEOUT;
}
+/*
+ * Configure the FPGA for logic-analyzer mode.
+ */
+static int sigma_fpga_init_la(struct dev_context *devc)
+{
+ /* Initialize the logic analyzer mode. */
+ uint8_t logic_mode_start[] = {
+ REG_ADDR_LOW | (READ_ID & 0xf),
+ REG_ADDR_HIGH | (READ_ID >> 8),
+ REG_READ_ADDR, /* Read ID register. */
+
+ REG_ADDR_LOW | (WRITE_TEST & 0xf),
+ REG_DATA_LOW | 0x5,
+ REG_DATA_HIGH_WRITE | 0x5,
+ REG_READ_ADDR, /* Read scratch register. */
+
+ REG_DATA_LOW | 0xa,
+ REG_DATA_HIGH_WRITE | 0xa,
+ REG_READ_ADDR, /* Read scratch register. */
+
+ REG_ADDR_LOW | (WRITE_MODE & 0xf),
+ REG_DATA_LOW | 0x0,
+ REG_DATA_HIGH_WRITE | 0x8,
+ };
+
+ uint8_t result[3];
+ int ret;
+
+ /* Initialize the logic analyzer mode. */
+ sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
+
+ /* Expect a 3 byte reply since we issued three READ requests. */
+ ret = sigma_read(result, 3, devc);
+ if (ret != 3)
+ goto err;
+
+ if (result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa)
+ goto err;
+
+ return SR_OK;
+err:
+ sr_err("Configuration failed. Invalid reply received.");
+ return SR_ERR;
+}
+
+/*
+ * Read the firmware from a file and transform it into a series of bitbang
+ * pulses used to program the FPGA. Note that the *bb_cmd must be free()'d
+ * by the caller of this function.
+ */
+static int sigma_fw_2_bitbang(const char *filename,
+ uint8_t **bb_cmd, gsize *bb_cmd_size)
+{
+ GMappedFile *file;
+ GError *error;
+ gsize i, file_size, bb_size;
+ gchar *firmware;
+ uint8_t *bb_stream, *bbs;
+ uint32_t imm;
+ int bit, v;
+ int ret = SR_OK;
+
+ /*
+ * Map the file and make the mapped buffer writable.
+ * NOTE: Using writable=TRUE does _NOT_ mean that file that is mapped
+ * will be modified. It will not be modified until someone uses
+ * g_file_set_contents() on it.
+ */
+ error = NULL;
+ file = g_mapped_file_new(filename, TRUE, &error);
+ g_assert_no_error(error);
+
+ file_size = g_mapped_file_get_length(file);
+ firmware = g_mapped_file_get_contents(file);
+ g_assert(firmware);
+
+ /* Weird magic transformation below, I have no idea what it does. */
+ imm = 0x3f6df2ab;
+ for (i = 0; i < file_size; i++) {
+ imm = (imm + 0xa853753) % 177 + (imm * 0x8034052);
+ firmware[i] ^= imm & 0xff;
+ }
+
+ /*
+ * Now that the firmware is "transformed", we will transcribe the
+ * firmware blob into a sequence of toggles of the Dx wires. This
+ * sequence will be fed directly into the Sigma, which must be in
+ * the FPGA bitbang programming mode.
+ */
+
+ /* Each bit of firmware is transcribed as two toggles of Dx wires. */
+ bb_size = file_size * 8 * 2;
+ bb_stream = (uint8_t *)g_try_malloc(bb_size);
+ if (!bb_stream) {
+ sr_err("%s: Failed to allocate bitbang stream", __func__);
+ ret = SR_ERR_MALLOC;
+ goto exit;
+ }
+
+ bbs = bb_stream;
+ for (i = 0; i < file_size; i++) {
+ for (bit = 7; bit >= 0; bit--) {
+ v = (firmware[i] & (1 << bit)) ? 0x40 : 0x00;
+ *bbs++ = v | 0x01;
+ *bbs++ = v;
+ }
+ }
+
+ /* The transformation completed successfully, return the result. */
+ *bb_cmd = bb_stream;
+ *bb_cmd_size = bb_size;
+
+exit:
+ g_mapped_file_unref(file);
+ return ret;
+}
+
static int upload_firmware(int firmware_idx, struct dev_context *devc)
{
int ret;
unsigned char *buf;
unsigned char pins;
size_t buf_size;
- unsigned char result[32];
const char *firmware = sigma_firmware_files[firmware_idx];
struct ftdi_context *ftdic = &devc->ftdic;
ftdi_usb_purge_buffers(ftdic);
/* Discard garbage. */
- while (1 == sigma_read(&pins, 1, devc))
+ while (sigma_read(&pins, 1, devc) == 1)
;
- /* Initialize the logic analyzer mode. */
- sigma_write(logic_mode_start, sizeof(logic_mode_start), devc);
-
- /* Expect a 3 byte reply. */
- ret = sigma_read(result, 3, devc);
- if (ret != 3 ||
- result[0] != 0xa6 || result[1] != 0x55 || result[2] != 0xaa) {
- sr_err("Configuration failed. Invalid reply received.");
- return SR_ERR;
- }
+ /* Initialize the FPGA for logic-analyzer mode. */
+ ret = sigma_fpga_init_la(devc);
+ if (ret != SR_OK)
+ return ret;
devc->cur_firmware = firmware_idx;
{
struct dev_context *devc;
uint64_t num_samples;
- int ret;
+ int ret = 0;
(void)cg;
}
/* Software trigger to determine exact trigger position. */
-static int get_trigger_offset(uint16_t *samples, uint16_t last_sample,
+static int get_trigger_offset(uint8_t *samples, uint16_t last_sample,
struct sigma_trigger *t)
{
int i;
+ uint16_t sample = 0;
for (i = 0; i < 8; ++i) {
if (i > 0)
- last_sample = samples[i-1];
+ last_sample = sample;
+ sample = samples[2 * i] | (samples[2 * i + 1] << 8);
/* Simple triggers. */
- if ((samples[i] & t->simplemask) != t->simplevalue)
+ if ((sample & t->simplemask) != t->simplevalue)
continue;
/* Rising edge. */
- if ((last_sample & t->risingmask) != 0 || (samples[i] &
- t->risingmask) != t->risingmask)
+ if (((last_sample & t->risingmask) != 0) ||
+ ((sample & t->risingmask) != t->risingmask))
continue;
/* Falling edge. */
if ((last_sample & t->fallingmask) != t->fallingmask ||
- (samples[i] & t->fallingmask) != 0)
+ (sample & t->fallingmask) != 0)
continue;
break;
return i & 0x7;
}
+
+/*
+ * Return the timestamp of "DRAM cluster".
+ */
+static uint16_t sigma_dram_cluster_ts(struct sigma_dram_cluster *cluster)
+{
+ return (cluster->timestamp_hi << 8) | cluster->timestamp_lo;
+}
+
+static void sigma_decode_dram_cluster(struct sigma_dram_cluster *dram_cluster,
+ unsigned int events_in_cluster,
+ struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+ struct sigma_state *ss = &devc->state;
+ struct sr_datafeed_packet packet;
+ struct sr_datafeed_logic logic;
+ uint16_t tsdiff, ts;
+ uint8_t samples[2048];
+ unsigned int i;
+
+ int triggerts = -1;
+
+ ts = sigma_dram_cluster_ts(dram_cluster);
+ tsdiff = ts - ss->lastts;
+ ss->lastts = ts;
+
+ packet.type = SR_DF_LOGIC;
+ packet.payload = &logic;
+ logic.unitsize = 2;
+ logic.data = samples;
+
+ /*
+ * First of all, send Sigrok a copy of the last sample from
+ * previous cluster as many times as needed to make up for
+ * the differential characteristics of data we get from the
+ * Sigma. Sigrok needs one sample of data per period.
+ *
+ * One DRAM cluster contains a timestamp and seven samples,
+ * the units of timestamp are "devc->period_ps" , the first
+ * sample in the cluster happens at the time of the timestamp
+ * and the remaining samples happen at timestamp +1...+6 .
+ */
+ for (ts = 0; ts < tsdiff - (EVENTS_PER_CLUSTER - 1); ts++) {
+ i = ts % 1024;
+ samples[2 * i + 0] = ss->lastsample & 0xff;
+ samples[2 * i + 1] = ss->lastsample >> 8;
+
+ /*
+ * If we have 1024 samples ready or we're at the
+ * end of submitting the padding samples, submit
+ * the packet to Sigrok.
+ */
+ if ((i == 1023) || (ts == (tsdiff - EVENTS_PER_CLUSTER))) {
+ logic.length = (i + 1) * logic.unitsize;
+ sr_session_send(devc->cb_data, &packet);
+ }
+ }
+
+ /*
+ * Parse the samples in current cluster and prepare them
+ * to be submitted to Sigrok.
+ */
+ for (i = 0; i < events_in_cluster; i++) {
+ samples[2 * i + 1] = dram_cluster->samples[i].sample_lo;
+ samples[2 * i + 0] = dram_cluster->samples[i].sample_hi;
+ }
+
+ /* Send data up to trigger point (if triggered). */
+ int trigger_offset = 0;
+ if ((int)i == triggerts) {
+ /*
+ * Trigger is not always accurate to sample because of
+ * pipeline delay. However, it always triggers before
+ * the actual event. We therefore look at the next
+ * samples to pinpoint the exact position of the trigger.
+ */
+ trigger_offset = get_trigger_offset(samples,
+ ss->lastsample, &devc->trigger);
+
+ if (trigger_offset > 0) {
+ packet.type = SR_DF_LOGIC;
+ logic.length = trigger_offset * logic.unitsize;
+ sr_session_send(devc->cb_data, &packet);
+ events_in_cluster -= trigger_offset;
+ }
+
+ /* Only send trigger if explicitly enabled. */
+ if (devc->use_triggers) {
+ packet.type = SR_DF_TRIGGER;
+ sr_session_send(devc->cb_data, &packet);
+ }
+ }
+
+ if (events_in_cluster > 0) {
+ packet.type = SR_DF_LOGIC;
+ logic.length = events_in_cluster * logic.unitsize;
+ logic.data = samples + (trigger_offset * logic.unitsize);
+ sr_session_send(devc->cb_data, &packet);
+ }
+
+ ss->lastsample =
+ samples[2 * (events_in_cluster - 1) + 0] |
+ (samples[2 * (events_in_cluster - 1) + 1] << 8);
+
+}
+
/*
* Decode chunk of 1024 bytes, 64 clusters, 7 events per cluster.
* Each event is 20ns apart, and can contain multiple samples.
* For 50 MHz and below, events contain one sample for each channel,
* spread 20 ns apart.
*/
-static int decode_chunk_ts(uint8_t *buf, uint16_t *lastts,
- uint16_t *lastsample, int triggerpos,
- uint16_t limit_chunk, void *cb_data)
+static int decode_chunk_ts(struct sigma_dram_line *dram_line, int triggerpos,
+ uint16_t events_in_line, void *cb_data)
{
+ struct sigma_dram_cluster *dram_cluster;
struct sr_dev_inst *sdi = cb_data;
struct dev_context *devc = sdi->priv;
- uint16_t tsdiff, ts;
- uint16_t samples[65536 * devc->samples_per_event];
- struct sr_datafeed_packet packet;
- struct sr_datafeed_logic logic;
- int i, j, k, l, numpad, tosend;
- size_t n = 0, sent = 0;
- int clustersize = EVENTS_PER_CLUSTER * devc->samples_per_event;
- uint16_t *event;
- uint16_t cur_sample;
+ unsigned int clusters_in_line =
+ (events_in_line + (EVENTS_PER_CLUSTER - 1)) / EVENTS_PER_CLUSTER;
+ unsigned int events_in_cluster;
+ unsigned int i;
int triggerts = -1;
/* Check if trigger is in this chunk. */
triggerpos = 0;
/* Find in which cluster the trigger occured. */
- triggerts = triggerpos / 7;
+ triggerts = triggerpos / EVENTS_PER_CLUSTER;
}
- /* For each ts. */
- for (i = 0; i < 64; ++i) {
- ts = *(uint16_t *) &buf[i * 16];
- tsdiff = ts - *lastts;
- *lastts = ts;
+ /* For each full DRAM cluster. */
+ for (i = 0; i < clusters_in_line; i++) {
+ dram_cluster = &dram_line->cluster[i];
- /* Decode partial chunk. */
- if (limit_chunk && ts > limit_chunk)
- return SR_OK;
+ /* The last cluster might not be full. */
+ if ((i == clusters_in_line - 1) &&
+ (events_in_line % EVENTS_PER_CLUSTER)) {
+ events_in_cluster = events_in_line % EVENTS_PER_CLUSTER;
+ } else {
+ events_in_cluster = EVENTS_PER_CLUSTER;
+ }
- /* Pad last sample up to current point. */
- numpad = tsdiff * devc->samples_per_event - clustersize;
- if (numpad > 0) {
- for (j = 0; j < numpad; ++j)
- samples[j] = *lastsample;
+ sigma_decode_dram_cluster(dram_cluster, events_in_cluster, sdi);
+ }
- n = numpad;
- }
+ return SR_OK;
+}
- /* Send samples between previous and this timestamp to sigrok. */
- sent = 0;
- while (sent < n) {
- tosend = MIN(2048, n - sent);
+static int download_capture(struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
+ const int chunks_per_read = 32;
+ struct sigma_dram_line *dram_line;
+ int bufsz;
+ uint32_t stoppos, triggerpos;
+ struct sr_datafeed_packet packet;
+ uint8_t modestatus;
- packet.type = SR_DF_LOGIC;
- packet.payload = &logic;
- logic.length = tosend * sizeof(uint16_t);
- logic.unitsize = 2;
- logic.data = samples + sent;
- sr_session_send(devc->cb_data, &packet);
+ uint32_t i;
+ uint32_t dl_lines_total, dl_lines_curr, dl_lines_done;
+ uint32_t dl_events_in_line = 64 * 7;
+ uint32_t trg_line = ~0;
- sent += tosend;
- }
- n = 0;
+ dram_line = g_try_malloc0(chunks_per_read * sizeof(*dram_line));
+ if (!dram_line)
+ return FALSE;
- event = (uint16_t *) &buf[i * 16 + 2];
- cur_sample = 0;
+ sr_info("Downloading sample data.");
- /* For each event in cluster. */
- for (j = 0; j < 7; ++j) {
+ /* Stop acquisition. */
+ sigma_set_register(WRITE_MODE, 0x11, devc);
- /* For each sample in event. */
- for (k = 0; k < devc->samples_per_event; ++k) {
- cur_sample = 0;
+ /* Set SDRAM Read Enable. */
+ sigma_set_register(WRITE_MODE, 0x02, devc);
- /* For each channel. */
- for (l = 0; l < devc->num_channels; ++l)
- cur_sample |= (!!(event[j] & (1 << (l *
- devc->samples_per_event + k)))) << l;
+ /* Get the current position. */
+ sigma_read_pos(&stoppos, &triggerpos, devc);
- samples[n++] = cur_sample;
- }
- }
+ /* Check if trigger has fired. */
+ modestatus = sigma_get_register(READ_MODE, devc);
+ if (modestatus & 0x20)
+ trg_line = triggerpos >> 9;
- /* Send data up to trigger point (if triggered). */
- sent = 0;
- if (i == triggerts) {
- /*
- * Trigger is not always accurate to sample because of
- * pipeline delay. However, it always triggers before
- * the actual event. We therefore look at the next
- * samples to pinpoint the exact position of the trigger.
- */
- tosend = get_trigger_offset(samples, *lastsample,
- &devc->trigger);
-
- if (tosend > 0) {
- packet.type = SR_DF_LOGIC;
- packet.payload = &logic;
- logic.length = tosend * sizeof(uint16_t);
- logic.unitsize = 2;
- logic.data = samples;
- sr_session_send(devc->cb_data, &packet);
-
- sent += tosend;
- }
+ /*
+ * Determine how many 1024b "DRAM lines" do we need to read from the
+ * Sigma so we have a complete set of samples. Note that the last
+ * line can be only partial, containing less than 64 clusters.
+ */
+ dl_lines_total = (stoppos >> 9) + 1;
- /* Only send trigger if explicitly enabled. */
- if (devc->use_triggers) {
- packet.type = SR_DF_TRIGGER;
- sr_session_send(devc->cb_data, &packet);
- }
+ dl_lines_done = 0;
+
+ while (dl_lines_total > dl_lines_done) {
+ /* We can download only up-to 32 DRAM lines in one go! */
+ dl_lines_curr = MIN(chunks_per_read, dl_lines_total);
+
+ bufsz = sigma_read_dram(dl_lines_done, dl_lines_curr,
+ (uint8_t *)dram_line, devc);
+ /* TODO: Check bufsz. For now, just avoid compiler warnings. */
+ (void)bufsz;
+
+ /* This is the first DRAM line, so find the initial timestamp. */
+ if (dl_lines_done == 0) {
+ devc->state.lastts =
+ sigma_dram_cluster_ts(&dram_line[0].cluster[0]);
+ devc->state.lastsample = 0;
}
- /* Send rest of the chunk to sigrok. */
- tosend = n - sent;
+ for (i = 0; i < dl_lines_curr; i++) {
+ int trigger_line = -1;
+ /* The last "DRAM line" can be only partially full. */
+ if (dl_lines_done + i == dl_lines_total - 1)
+ dl_events_in_line = stoppos & 0x1ff;
- if (tosend > 0) {
- packet.type = SR_DF_LOGIC;
- packet.payload = &logic;
- logic.length = tosend * sizeof(uint16_t);
- logic.unitsize = 2;
- logic.data = samples + sent;
- sr_session_send(devc->cb_data, &packet);
+ /* Test if the trigger happened on this line. */
+ if (dl_lines_done + i == trg_line)
+ trigger_line = trg_line;
+
+ decode_chunk_ts(dram_line + i, trigger_line,
+ dl_events_in_line, sdi);
}
- *lastsample = samples[n - 1];
+ dl_lines_done += dl_lines_curr;
}
- return SR_OK;
-}
+ /* All done. */
+ packet.type = SR_DF_END;
+ sr_session_send(sdi, &packet);
-static void download_capture(struct sr_dev_inst *sdi)
-{
- struct dev_context *devc;
- const int chunks_per_read = 32;
- unsigned char buf[chunks_per_read * CHUNK_SIZE];
- int bufsz, i, numchunks, newchunks;
+ dev_acquisition_stop(sdi, sdi);
- sr_info("Downloading sample data.");
+ g_free(dram_line);
- devc = sdi->priv;
- devc->state.chunks_downloaded = 0;
- numchunks = (devc->state.stoppos + 511) / 512;
- newchunks = MIN(chunks_per_read, numchunks - devc->state.chunks_downloaded);
-
- bufsz = sigma_read_dram(devc->state.chunks_downloaded, newchunks, buf, devc);
- /* TODO: Check bufsz. For now, just avoid compiler warnings. */
- (void)bufsz;
-
- /* Find first ts. */
- if (devc->state.chunks_downloaded == 0) {
- devc->state.lastts = RL16(buf) - 1;
- devc->state.lastsample = 0;
- }
+ return TRUE;
+}
+
+/*
+ * Handle the Sigma when in CAPTURE mode. This function checks:
+ * - Sampling time ended
+ * - DRAM capacity overflow
+ * This function triggers download of the samples from Sigma
+ * in case either of the above conditions is true.
+ */
+static int sigma_capture_mode(struct sr_dev_inst *sdi)
+{
+ struct dev_context *devc = sdi->priv;
- /* Decode chunks and send them to sigrok. */
- for (i = 0; i < newchunks; ++i) {
- int limit_chunk = 0;
+ uint64_t running_msec;
+ struct timeval tv;
- /* The last chunk may potentially be only in part. */
- if (devc->state.chunks_downloaded == numchunks - 1) {
- /* Find the last valid timestamp */
- limit_chunk = devc->state.stoppos % 512 + devc->state.lastts;
- }
+ uint32_t stoppos, triggerpos;
- if (devc->state.chunks_downloaded + i == devc->state.triggerchunk)
- decode_chunk_ts(buf + (i * CHUNK_SIZE),
- &devc->state.lastts,
- &devc->state.lastsample,
- devc->state.triggerpos & 0x1ff,
- limit_chunk, sdi);
- else
- decode_chunk_ts(buf + (i * CHUNK_SIZE),
- &devc->state.lastts,
- &devc->state.lastsample,
- -1, limit_chunk, sdi);
+ /* Check if the selected sampling duration passed. */
+ gettimeofday(&tv, 0);
+ running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
+ (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
+ if (running_msec >= devc->limit_msec)
+ return download_capture(sdi);
- ++devc->state.chunks_downloaded;
- }
+ /* Get the position in DRAM to which the FPGA is writing now. */
+ sigma_read_pos(&stoppos, &triggerpos, devc);
+ /* Test if DRAM is full and if so, download the data. */
+ if ((stoppos >> 9) == 32767)
+ return download_capture(sdi);
+ return TRUE;
}
static int receive_data(int fd, int revents, void *cb_data)
{
struct sr_dev_inst *sdi;
struct dev_context *devc;
- struct sr_datafeed_packet packet;
- uint64_t running_msec;
- struct timeval tv;
- int numchunks;
- uint8_t modestatus;
(void)fd;
(void)revents;
sdi = cb_data;
devc = sdi->priv;
- /* Get the current position. */
- sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
-
if (devc->state.state == SIGMA_IDLE)
return TRUE;
- if (devc->state.state == SIGMA_CAPTURE) {
- numchunks = (devc->state.stoppos + 511) / 512;
-
- /* Check if the timer has expired, or memory is full. */
- gettimeofday(&tv, 0);
- running_msec = (tv.tv_sec - devc->start_tv.tv_sec) * 1000 +
- (tv.tv_usec - devc->start_tv.tv_usec) / 1000;
-
- if (running_msec < devc->limit_msec && numchunks < 32767)
- /* Still capturing. */
- return TRUE;
-
- /* Stop acquisition. */
- sigma_set_register(WRITE_MODE, 0x11, devc);
-
- /* Set SDRAM Read Enable. */
- sigma_set_register(WRITE_MODE, 0x02, devc);
-
- /* Get the current position. */
- sigma_read_pos(&devc->state.stoppos, &devc->state.triggerpos, devc);
-
- /* Check if trigger has fired. */
- modestatus = sigma_get_register(READ_MODE, devc);
- if (modestatus & 0x20)
- devc->state.triggerchunk = devc->state.triggerpos / 512;
- else
- devc->state.triggerchunk = -1;
-
- /* Transfer captured data from device. */
- download_capture(sdi);
-
- /* All done. */
- packet.type = SR_DF_END;
- sr_session_send(sdi, &packet);
-
- dev_acquisition_stop(sdi, sdi);
- }
+ if (devc->state.state == SIGMA_CAPTURE)
+ return sigma_capture_mode(sdi);
return TRUE;
}
projects / libsigrok.git / blobdiff