id = 'usb_signalling'
name = 'USB signalling'
longname = 'Universal Serial Bus (LS/FS) signalling'
- desc = 'USB (low-speed and full-speed) signalling protocol.'
+ desc = 'USB (low-speed/full-speed) signalling protocol.'
license = 'gplv2+'
inputs = ['logic']
outputs = ['usb_signalling']
+ tags = ['PC']
channels = (
{'id': 'dp', 'name': 'D+', 'desc': 'USB D+ signal'},
{'id': 'dm', 'name': 'D-', 'desc': 'USB D- signal'},
)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.samplerate = None
self.oldsym = 'J' # The "idle" state is J.
self.ss_block = None
self.put(s, e, self.out_ann, data)
def set_new_target_samplenum(self):
- self.samplepos += self.bitwidth;
+ self.samplepos += self.bitwidth
self.samplenum_target = int(self.samplepos)
self.samplenum_lastedge = self.samplenum_edge
self.samplenum_edge = int(self.samplepos - (self.bitwidth / 2))
raise SamplerateError('Cannot decode without samplerate.')
# Seed internal state from the very first sample.
- pins = self.wait({'skip': 1})
+ pins = self.wait()
sym = symbols[self.options['signalling']][pins]
self.handle_idle(sym)
elif self.state == 'GET EOP':
self.get_eop(sym)
elif self.state == 'WAIT IDLE':
- pins = self.wait({'skip': 1})
- if pins == (0, 0):
- continue
+ # Skip "all-low" input. Wait for high level on either DP or DM.
+ pins = self.wait()
+ while not pins[0] and not pins[1]:
+ pins = self.wait([{0: 'h'}, {1: 'h'}])
if self.samplenum - self.samplenum_lastedge > 1:
sym = symbols[self.options['signalling']][pins]
self.handle_idle(sym)