import sigrokdecode as srd
-# States
-SE0, J, K, SE1 = 0, 1, 2, 3
-
-# ...
+# Symbols (used as states of our state machine, too)
syms = {
- (0, 0): SE0,
- (1, 0): J,
- (0, 1): K,
- (1, 1): SE1,
+ # (<dp>, <dm>): <state>
+ (0, 0): 'SE0',
+ (1, 0): 'J',
+ (0, 1): 'K',
+ (1, 1): 'SE1',
}
# ...
dev = bitstr_to_num(data[:7])
ep = bitstr_to_num(data[7:])
data = 'DEV %d EP %d' % (dev, ep)
-
elif pid in ('DATA0', 'DATA1'):
data = packet[16:-16]
tmp = ''
id = 'usb'
name = 'USB'
longname = 'Universal Serial Bus'
- desc = 'Universal Serial Bus'
- longdesc = '...longdesc...'
+ desc = 'USB 1.x (full-speed) serial protocol.'
license = 'gplv2+'
inputs = ['logic']
outputs = ['usb']
optional_probes = []
options = {}
annotations = [
- ['TODO', 'TODO']
+ ['Text', 'Human-readable text']
]
def __init__(self):
- pass
+ self.sym = 'J'
+ self.samplenum = 0
+ self.scount = 0
+ self.packet = ''
def start(self, metadata):
- self.rate = metadata['samplerate']
+ self.samplerate = metadata['samplerate']
+
+ if self.samplerate < 48000000:
+ raise Exception('Samplerate (%d) not sufficient for USB '
+ 'decoding, need at least 48MHz' % self.samplerate)
# self.out_proto = self.add(srd.OUTPUT_PROTO, 'usb')
self.out_ann = self.add(srd.OUTPUT_ANN, 'usb')
- if self.rate < 48000000:
- raise Exception('Sample rate (%d) not sufficient for USB '
- 'decoding, need at least 48MHz' % self.rate)
-
- # Initialise decoder state.
- self.sym = J
- self.scount = 0
- self.packet = ''
-
def report(self):
pass
def decode(self, ss, es, data):
- for (samplenum, (dm, dp)) in data:
+ for (self.samplenum, (dp, dm)) in data:
+ # Note: self.samplenum is the absolute sample number, whereas
+ # self.scount only counts the number of samples since the
+ # last change in the D+/D- lines.
self.scount += 1
sym = syms[dp, dm]
- # ...
+ # Wait for a symbol change (i.e., change in D+/D- lines).
if sym == self.sym:
continue
if self.scount == 1:
- # We ignore single sample width pulses.
- # I sometimes get these with the OLS.
+ # We ignore single sample width "pulses", i.e., symbol changes
+ # (D+/D- line changes). I sometimes get these with the OLS.
self.sym = sym
self.scount = 0
continue
# How many bits since the last transition?
- if self.packet != '' or self.sym != J:
- bitcount = int((self.scount - 1) * 12000000 / self.rate)
+ if self.packet != '' or self.sym != 'J':
+ bitcount = int((self.scount - 1) * 12000000 / self.samplerate)
else:
bitcount = 0
- if self.sym == SE0:
+ if self.sym == 'SE0':
if bitcount == 1:
# End-Of-Packet (EOP)
self.put(0, 0, self.out_ann,
self.packet += '1' * bitcount
# Handle bit stuffing.
- if bitcount < 6 and sym != SE0:
+ if bitcount < 6 and sym != 'SE0':
self.packet += '0'
elif bitcount > 6:
self.put(0, 0, self.out_ann, [0, ['BIT STUFF ERROR']])