srd: Add SRD_ERR_BUG.

[libsigrokdecode.git] / decoders / uart.py

diff --git a/decoders/uart.py b/decoders/uart.py
index efc1756149e568f5d0c57048396b355c1939af27..dac7017cbcbe68d14be74a112db82b5adb402c55 100644 (file)
--- a/decoders/uart.py
+++ b/decoders/uart.py
@@ -94,7 +94,7 @@
 # TODO: URLs
 #
 
-import sigrok
+import sigrokdecode
 
 # States
 WAIT_FOR_START_BIT = 0
@@ -127,17 +127,6 @@ DATA_FORMAT_HEX = 1
 # TODO: Remove me later.
 quick_hack = 1
 
-class Sample():
-    def __init__(self, data):
-        self.data = data
-    def probe(self, probe):
-        s = ord(self.data[probe / 8]) & (1 << (probe % 8))
-        return True if s else False
-
-def sampleiter(data, unitsize):
-    for i in range(0, len(data), unitsize):
-        yield(Sample(data[i:i+unitsize]))
-
 # Given a parity type to check (odd, even, zero, one), the value of the
 # parity bit, the value of the data, and the length of the data (5-9 bits,
 # usually 8 bits) return True if the parity is correct, False otherwise.
@@ -161,7 +150,7 @@ def parity_ok(parity_type, parity_bit, data, num_data_bits):
     else:
         raise Exception('Invalid parity type: %d' % parity_type)
 
-class Decoder(sigrok.Decoder):
+class Decoder(sigrokdecode.Decoder):
     id = 'uart'
     name = 'UART'
     longname = 'Universal Asynchronous Receiver/Transmitter (UART)'
@@ -172,14 +161,12 @@ class Decoder(sigrok.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['uart']
-    probes = {
+    probes = [
         # Allow specifying only one of the signals, e.g. if only one data
         # direction exists (or is relevant).
-        ## 'rx': {'ch': 0, 'name': 'RX', 'desc': 'UART receive line'},
-        ## 'tx': {'ch': 1, 'name': 'TX', 'desc': 'UART transmit line'},
-        'rx': 0,
-        'tx': 1,
-    }
+        {'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
+        {'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
+    ]
     options = {
         'baudrate': ['UART baud rate', 115200],
         'num_data_bits': ['Data bits', 8], # Valid: 5-9.
@@ -193,7 +180,8 @@ class Decoder(sigrok.Decoder):
     }
 
     def __init__(self, **kwargs):
-        self.probes = Decoder.probes.copy()
+        self.output_protocol = None
+        self.output_annotation = None
 
         # Set defaults, can be overridden in 'start'.
         self.baudrate = 115200
@@ -215,18 +203,13 @@ class Decoder(sigrok.Decoder):
         # Initial state.
         self.staterx = WAIT_FOR_START_BIT
 
-        # Get the channel/probe number of the RX/TX signals.
-        ## self.rx_bit = self.probes['rx']['ch']
-        ## self.tx_bit = self.probes['tx']['ch']
-        self.rx_bit = self.probes['rx']
-        self.tx_bit = self.probes['tx']
-
         self.oldrx = None
         self.oldtx = None
 
     def start(self, metadata):
-        self.unitsize = metadata['unitsize']
         self.samplerate = metadata['samplerate']
+        # self.output_protocol = self.output_new(2)
+        self.output_annotation = self.output_new(1)
 
         # TODO
         ### self.baudrate = metadata['baudrate']
@@ -370,9 +353,7 @@ class Decoder(sigrok.Decoder):
     # TODO: Currently only supports 1 stop bit.
     def get_stop_bits(self, signal):
         # Skip samples until we're in the middle of the stop bit(s).
-        skip_parity = 0
-        if self.parity != PARITY_NONE:
-            skip_parity = 1
+        skip_parity = 0 if self.parity == PARITY_NONE else 1
         if not self.reached_bit(self.num_data_bits + 1 + skip_parity):
             return []
 
@@ -392,15 +373,11 @@ class Decoder(sigrok.Decoder):
              'data': None, 'ann': 'Stop bit'}]
         return o
 
-    def decode(self, data):
-        """UART protocol decoder"""
-
+    def decode(self, timeoffset, duration, data): # TODO
         out = []
 
-        for sample in sampleiter(data["data"], self.unitsize):
-
-            # TODO: Eliminate the need for ord().
-            s = ord(sample.data)
+        # for (samplenum, (rx, tx)) in data:
+        for (samplenum, (rx,)) in data:
 
             # TODO: Start counting at 0 or 1? Increase before or after?
             self.samplenum += 1
@@ -408,14 +385,10 @@ class Decoder(sigrok.Decoder):
             # First sample: Save RX/TX value.
             if self.oldrx == None:
                 # Get RX/TX bit values (0/1 for low/high) of the first sample.
-                self.oldrx = (s & (1 << self.rx_bit)) >> self.rx_bit
-                # self.oldtx = (s & (1 << self.tx_bit)) >> self.tx_bit
+                self.oldrx = rx
+                # self.oldtx = tx
                 continue
 
-            # Get RX/TX bit values (0/1 for low/high).
-            rx = (s & (1 << self.rx_bit)) >> self.rx_bit
-            # tx = (s & (1 << self.tx_bit)) >> self.tx_bit
-
             # State machine.
             if self.staterx == WAIT_FOR_START_BIT:
                 self.wait_for_start_bit(self.oldrx, rx)
@@ -435,5 +408,6 @@ class Decoder(sigrok.Decoder):
             # self.oldtx = tx
 
         if out != []:
-            self.put(out)
+            # self.put(0, 0, self.output_protocol, out_proto)
+            self.put(0, 0, self.output_annotation, out)