import sigrokdecode as srd
'''
-Protocol output format:
+OUTPUT_PYTHON format:
UART packet:
[<packet-type>, <rxtx>, <packet-data>]
license = 'gplv2+'
inputs = ['logic']
outputs = ['uart']
- probes = [
+ probes = []
+ optional_probes = [
# Allow specifying only one of the signals, e.g. if only one data
# direction exists (or is relevant).
{'id': 'rx', 'name': 'RX', 'desc': 'UART receive line'},
{'id': 'tx', 'name': 'TX', 'desc': 'UART transmit line'},
]
- optional_probes = []
options = {
'baudrate': ['Baud rate', 115200],
'num_data_bits': ['Data bits', 8], # Valid: 5-9.
# TODO: Options to invert the signal(s).
}
annotations = [
- ['rx-data', 'UART RX data'],
- ['tx-data', 'UART TX data'],
- ['start-bits', 'UART start bits'],
- ['parity-bits', 'UART parity bits'],
- ['stop-bits', 'UART stop bits'],
- ['warnings', 'Warnings'],
+ ['rx-data', 'RX data'],
+ ['tx-data', 'TX data'],
+ ['rx-start-bits', 'RX start bits'],
+ ['tx-start-bits', 'TX start bits'],
+ ['rx-parity-bits', 'RX parity bits'],
+ ['tx-parity-bits', 'TX parity bits'],
+ ['rx-stop-bits', 'RX stop bits'],
+ ['tx-stop-bits', 'TX stop bits'],
+ ['rx-warnings', 'RX warnings'],
+ ['tx-warnings', 'TX warnings'],
]
+ annotation_rows = (
+ ('rx-data', 'RX', (0, 2, 4, 6)),
+ ('tx-data', 'TX', (1, 3, 5, 7)),
+ ('rx-warnings', 'RX warnings', (8,)),
+ ('tx-warnings', 'TX warnings', (9,)),
+ )
binary = (
('rx', 'RX dump'),
('tx', 'TX dump'),
def putp(self, data):
s, halfbit = self.samplenum, int(self.bit_width / 2)
- self.put(s - halfbit, s + halfbit, self.out_proto, data)
+ self.put(s - halfbit, s + halfbit, self.out_python, data)
def putbin(self, rxtx, data):
s, halfbit = self.startsample[rxtx], int(self.bit_width / 2)
self.oldpins = [1, 1]
def start(self):
- self.out_proto = self.register(srd.OUTPUT_PYTHON)
+ self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_bin = self.register(srd.OUTPUT_BINARY)
self.out_ann = self.register(srd.OUTPUT_ANN)
self.state[rxtx] = 'GET DATA BITS'
self.putp(['STARTBIT', rxtx, self.startbit[rxtx]])
- self.putg([2, ['Start bit', 'Start', 'S']])
+ self.putg([rxtx + 2, ['Start bit', 'Start', 'S']])
def get_data_bits(self, rxtx, signal):
# Skip samples until we're in the middle of the desired data bit.
if parity_ok(self.options['parity_type'], self.paritybit[rxtx],
self.databyte[rxtx], self.options['num_data_bits']):
self.putp(['PARITYBIT', rxtx, self.paritybit[rxtx]])
- self.putg([3, ['Parity bit', 'Parity', 'P']])
+ self.putg([rxtx + 4, ['Parity bit', 'Parity', 'P']])
else:
# TODO: Return expected/actual parity values.
self.putp(['PARITY ERROR', rxtx, (0, 1)]) # FIXME: Dummy tuple...
- self.putg([5, ['Parity error', 'Parity err', 'PE']])
+ self.putg([rxtx + 8, ['Parity error', 'Parity err', 'PE']])
# TODO: Currently only supports 1 stop bit.
def get_stop_bits(self, rxtx, signal):
# Stop bits must be 1. If not, we report an error.
if self.stopbit1[rxtx] != 1:
self.putp(['INVALID STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([5, ['Frame error', 'Frame err', 'FE']])
+ self.putg([rxtx + 6, ['Frame error', 'Frame err', 'FE']])
# TODO: Abort? Ignore the frame? Other?
self.state[rxtx] = 'WAIT FOR START BIT'
self.putp(['STOPBIT', rxtx, self.stopbit1[rxtx]])
- self.putg([4, ['Stop bit', 'Stop', 'T']])
+ self.putg([rxtx + 4, ['Stop bit', 'Stop', 'T']])
def decode(self, ss, es, data):
if self.samplerate is None:
raise Exception("Cannot decode without samplerate.")
- # TODO: Either RX or TX could be omitted (optional probe).
for (self.samplenum, pins) in data:
# Note: Ignoring identical samples here for performance reasons
# continue
self.oldpins, (rx, tx) = pins, pins
+ # Either RX or TX (but not both) can be omitted.
+ has_pin = [rx in (0, 1), tx in (0, 1)]
+ if has_pin == [False, False]:
+ raise Exception('Either TX or RX (or both) pins required.')
+
# State machine.
for rxtx in (RX, TX):
+ # Don't try to handle RX (or TX) if not supplied.
+ if not has_pin[rxtx]:
+ continue
+
signal = rx if (rxtx == RX) else tx
if self.state[rxtx] == 'WAIT FOR START BIT':