self.device_id = -1
self.on_end_transaction = None
self.end_current_transaction()
+ self.writestate = 0
# Build dict mapping command keys to handler functions. Each
# command in 'cmds' (defined in lists.py) has a matching
def handle_wren(self, mosi, miso):
self.putx([Ann.WREN, self.cmd_ann_list()])
- self.state = None
+ self.writestate = 1
def handle_wrdi(self, mosi, miso):
- pass # TODO
+ self.putx([Ann.WRDI, self.cmd_ann_list()])
+ self.writestate = 0
def handle_rdid(self, mosi, miso):
if self.cmdstate == 1:
self.putx([Ann.BIT, [decode_status_reg(miso)]])
self.putx([Ann.FIELD, ['Status register']])
self.putc([Ann.RDSR, self.cmd_ann_list()])
+ # Set write latch state.
+ self.writestate = 1 if (miso & (1 << 1)) else 0
self.cmdstate += 1
def handle_rdsr2(self, mosi, miso):
self.emit_cmd_byte()
elif self.cmdstate == 2:
# Byte 2: Master sends status register 1.
- self.putx([Ann.BIT, [decode_status_reg(miso)]])
+ self.putx([Ann.BIT, [decode_status_reg(mosi)]])
self.putx([Ann.FIELD, ['Status register 1']])
+ # Set write latch state.
+ self.writestate = 1 if (miso & (1 << 1)) else 0
elif self.cmdstate == 3:
# Byte 3: Master sends status register 2.
# TODO: Decode status register 2 correctly.
- self.putx([Ann.BIT, [decode_status_reg(miso)]])
+ self.putx([Ann.BIT, [decode_status_reg(mosi)]])
self.putx([Ann.FIELD, ['Status register 2']])
self.es_cmd = self.es
self.putc([Ann.WRSR, self.cmd_ann_list()])
if self.cmdstate == 1:
# Byte 1: Master sends command ID.
self.emit_cmd_byte()
+ if self.writestate == 0:
+ self.putc([Ann.WARN, ['Warning: WREN might be missing']])
elif self.cmdstate in (2, 3, 4):
# Bytes 2/3/4: Master sends write address (24bits, MSB-first).
self.emit_addr_bytes(mosi)
self.cmdstate += 1
# TODO: Warn/abort if we don't see the necessary amount of bytes.
- # TODO: Warn if WREN was not seen before.
def handle_se(self, mosi, miso):
if self.cmdstate == 1:
# Byte 1: Master sends command ID.
self.emit_cmd_byte()
+ if self.writestate == 0:
+ self.putx([Ann.WARN, ['Warning: WREN might be missing']])
elif self.cmdstate in (2, 3, 4):
# Bytes 2/3/4: Master sends sector address (24bits, MSB-first).
self.emit_addr_bytes(mosi)
pass # TODO
def handle_ce(self, mosi, miso):
- pass # TODO
+ self.putx([Ann.CE, self.cmd_ann_list()])
+ if self.writestate == 0:
+ self.putx([Ann.WARN, ['Warning: WREN might be missing']])
def handle_ce2(self, mosi, miso):
- pass # TODO
+ self.putx([Ann.CE2, self.cmd_ann_list()])
+ if self.writestate == 0:
+ self.putx([Ann.WARN, ['Warning: WREN might be missing']])
def handle_pp(self, mosi, miso):
# Page program: Master asserts CS#, sends PP command, sends 3-byte