CPOL_1 = 1 # Clock is high when inactive
# Clock phase options
-CPHA_0 = 0 # Data is valid on the rising clock edge
-CPHA_1 = 1 # Data is valid on the falling clock edge
+CPHA_0 = 0 # Data is valid on the leading clock edge
+CPHA_1 = 1 # Data is valid on the trailing clock edge
# Bit order options
MSB_FIRST = 0
LSB_FIRST = 1
+spi_mode = {
+ (0, 0): 0, # Mode 0
+ (0, 1): 1, # Mode 1
+ (1, 0): 2, # Mode 2
+ (1, 1): 3, # Mode 3
+}
+
# Annotation formats
ANN_HEX = 0
class Decoder(srd.Decoder):
id = 'spi'
name = 'SPI'
- longname = 'Serial Peripheral Interface (SPI) bus'
+ longname = 'Serial Peripheral Interface'
desc = '...desc...'
longdesc = '...longdesc...'
author = 'Gareth McMullin'
{'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
]
options = {
- 'cs_active_low': ['CS# active low', ACTIVE_LOW],
- 'clock_polarity': ['Clock polarity', CPOL_0],
- 'clock_phase': ['Clock phase', CPHA_0],
- 'bit_order': ['Bit order within the SPI data', MSB_FIRST],
- 'word_size': ['Word size of SPI data', 8], # 1-64?
+ 'cs_polarity': ['CS# polarity', ACTIVE_LOW],
+ 'cpol': ['Clock polarity', CPOL_0],
+ 'cpha': ['Clock phase', CPHA_0],
+ 'bitorder': ['Bit order within the SPI data', MSB_FIRST],
+ 'wordsize': ['Word size of SPI data', 8], # 1-64?
}
annotations = [
['Hex', 'SPI data bytes in hex format'],
self.misodata = 0
self.bytesreceived = 0
self.samplenum = -1
+ self.cs_was_deasserted_during_data_word = 0
+
+ # Set protocol decoder option defaults.
+ self.cs_polarity = Decoder.options['cs_polarity'][1]
+ self.cpol = Decoder.options['cpol'][1]
+ self.cpha = Decoder.options['cpha'][1]
+ self.bitorder = Decoder.options['bitorder'][1]
+ self.wordsize = Decoder.options['wordsize'][1]
def start(self, metadata):
self.out_proto = self.add(srd.OUTPUT_PROTO, 'spi')
self.samplenum += 1 # FIXME
- # Sample data on rising SCK edges.
+ # Ignore sample if the clock pin hasn't changed.
if sck == self.oldsck:
continue
+
self.oldsck = sck
- if sck == 0:
- continue
+
+ # Sample data on rising/falling clock edge (depends on mode).
+ mode = spi_mode[self.cpol, self.cpha]
+ if mode == 0 and sck == 0: # Sample on rising clock edge
+ continue
+ elif mode == 1 and sck == 1: # Sample on falling clock edge
+ continue
+ elif mode == 2 and sck == 1: # Sample on falling clock edge
+ continue
+ elif mode == 3 and sck == 0: # Sample on rising clock edge
+ continue
# If this is the first bit, save its sample number.
if self.bitcount == 0:
self.start_sample = samplenum
-
- # Receive bit into our shift register.
- if mosi == 1:
- self.mosidata |= 1 << (7 - self.bitcount)
- if miso == 1:
- self.misodata |= 1 << (7 - self.bitcount)
+ deasserted = cs if (self.cs_polarity == ACTIVE_LOW) else not c
+ if deasserted:
+ self.cs_was_deasserted_during_data_word = 1
+
+ # Receive MOSI bit into our shift register.
+ if self.bitorder == MSB_FIRST:
+ self.mosidata |= mosi << (self.wordsize - 1 - self.bitcount)
+ else:
+ self.mosidata |= mosi << self.bitcount
+
+ # Receive MISO bit into our shift register.
+ if self.bitorder == MSB_FIRST:
+ self.misodata |= miso << (self.wordsize - 1 - self.bitcount)
+ else:
+ self.misodata |= miso << self.bitcount
self.bitcount += 1
# Continue to receive if not a byte yet.
- if self.bitcount != 8:
+ if self.bitcount != self.wordsize:
continue
self.put(self.start_sample, self.samplenum, self.out_proto,
[ANN_HEX, ['MOSI: 0x%02x, MISO: 0x%02x' % (self.mosidata,
self.misodata)]])
+ if self.cs_was_deasserted_during_data_word:
+ self.put(self.start_sample, self.samplenum, self.out_ann,
+ [ANN_HEX, ['WARNING: CS# was deasserted during this '
+ 'SPI data byte!']])
+
# Reset decoder state.
self.mosidata = 0
self.misodata = 0