## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
-class Sample():
- def __init__(self, data):
- self.data = data
- def probe(self, probe):
- s = ord(self.data[probe / 8]) & (1 << (probe % 8))
- return True if s else False
+import sigrokdecode
-def sampleiter(data, unitsize):
- for i in range(0, len(data), unitsize):
- yield(Sample(data[i:i+unitsize]))
-
-class Decoder():
- name = 'SPI Decoder'
+class Decoder(sigrokdecode.Decoder):
+ id = 'spi'
+ name = 'SPI'
desc = '...desc...'
- longname = '...longname...'
+ longname = 'Serial Peripheral Interface (SPI) bus'
longdesc = '...longdesc...'
author = 'Gareth McMullin'
email = 'gareth@blacksphere.co.nz'
license = 'gplv2+'
inputs = ['logic']
outputs = ['spi']
- # Probe names with a set of defaults
- probes = {'sdata':0, 'sck':1}
+ probes = [
+ {'id': 'sdata', 'name': 'DATA', 'desc': 'SPI data line (MISO or MOSI)'},
+ {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
+ ]
options = {}
def __init__(self):
- self.probes = Decoder.probes.copy()
- self.oldsck = True
+ self.oldsck = 1
self.rxcount = 0
self.rxdata = 0
self.bytesreceived = 0
+ self.output_protocol = None
+ self.output_annotation = None
def start(self, metadata):
- self.unitsize = metadata['unitsize']
+ # self.output_protocol = self.output_new(2)
+ self.output_annotation = self.output_new(1)
def report(self):
return 'SPI: %d bytes received' % self.bytesreceived
- def decode(self, data):
- # We should accept a list of samples and iterate...
- for sample in sampleiter(data['data'], self.unitsize):
+ def decode(self, timeoffset, duration, data):
+ # HACK! At the moment the number of probes is not handled correctly.
+ # E.g. if an input file (-i foo.sr) has more than two probes enabled.
+ for (samplenum, (sdata, sck, x, y, z, a)) in data:
- sck = sample.probe(self.probes['sck'])
# Sample SDATA on rising SCK
if sck == self.oldsck:
continue
# If this is first bit, save timestamp
if self.rxcount == 0:
- self.time = data['time']
+ self.time = timeoffset # FIXME
# Receive bit into our shift register
- sdata = sample.probe(self.probes['sdata'])
if sdata:
self.rxdata |= 1 << (7 - self.rxcount)
self.rxcount += 1
continue
# Received a byte, pass up to sigrok
outdata = {'time':self.time,
- 'duration':data['time'] + data['duration'] - self.time,
+ 'duration':timeoffset + duration - self.time,
'data':self.rxdata,
'display':('%02X' % self.rxdata),
'type':'spi',
}
- sigrok.put(outdata)
+ # self.put(0, 0, self.output_protocol, out_proto)
+ self.put(0, 0, self.output_annotation, outdata)
# Reset decoder state
self.rxdata = 0
self.rxcount = 0
# Keep stats for summary
self.bytesreceived += 1
-if __name__ == '__main__':
- data = open('spi_dump.bin').read()
-
- # dummy class to keep Decoder happy for test
- class Sigrok():
- def put(self, data):
- print "\t", data
- sigrok = Sigrok()
-
- dec = Decoder(driver='ols', unitsize=1, starttime=0)
- dec.decode({'time':0, 'duration':len(data), 'data':data, 'type':'logic'})
-
- print dec.summary()
-else:
- import sigrok
-
-#Tested with:
-# sigrok-cli -d 0:samplerate=1000000:rle=on --time=1s -p 1,2 -a spidec
-