srd: uart: Move protocol docs to __init__.py.

[libsigrokdecode.git] / decoders / spi / spi.py

diff --git a/decoders/spi/spi.py b/decoders/spi/spi.py
index 7789e34c36cb96c1495a1e9af2fbf42753565331..ff186ddcf56d6280101c671317ee8173a8cf404c 100644 (file)
--- a/decoders/spi/spi.py
+++ b/decoders/spi/spi.py
@@ -66,7 +66,7 @@ class Decoder(srd.Decoder):
         {'id': 'sck', 'name': 'CLK', 'desc': 'SPI clock line'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'SPI CS (chip select) line'},
     ]
-    extra_probes = [] # TODO
+    optional_probes = [] # TODO
     options = {
         'cs_polarity': ['CS# polarity', ACTIVE_LOW],
         'cpol': ['Clock polarity', CPOL_0],
@@ -125,22 +125,24 @@ class Decoder(srd.Decoder):
                 if deasserted:
                     self.cs_was_deasserted_during_data_word = 1
 
+            ws = self.options['wordsize']
+
             # Receive MOSI bit into our shift register.
             if self.options['bitorder'] == MSB_FIRST:
-                self.mosidata |= mosi << (self.options['wordsize'] - 1 - self.bitcount)
+                self.mosidata |= mosi << (ws - 1 - self.bitcount)
             else:
                 self.mosidata |= mosi << self.bitcount
 
             # Receive MISO bit into our shift register.
             if self.options['bitorder'] == MSB_FIRST:
-                self.misodata |= miso << (self.options['wordsize'] - 1 - self.bitcount)
+                self.misodata |= miso << (ws - 1 - self.bitcount)
             else:
                 self.misodata |= miso << self.bitcount
 
             self.bitcount += 1
 
-            # Continue to receive if not a byte yet.
-            if self.bitcount != self.options['wordsize']:
+            # Continue to receive if not enough bits were received, yet.
+            if self.bitcount != ws:
                 continue
 
             self.put(self.start_sample, self.samplenum, self.out_proto,