license = 'gplv2+'
inputs = ['logic']
outputs = ['spi']
+ tags = ['Embedded/industrial']
channels = (
{'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
)
('miso-bits', 'MISO bits'),
('mosi-bits', 'MOSI bits'),
('warnings', 'Human-readable warnings'),
+ ('miso-transfer', 'MISO transfer'),
+ ('mosi-transfer', 'MOSI transfer'),
)
annotation_rows = (
- ('miso-data', 'MISO data', (0,)),
('miso-bits', 'MISO bits', (2,)),
- ('mosi-data', 'MOSI data', (1,)),
+ ('miso-data', 'MISO data', (0,)),
+ ('miso-transfer', 'MISO transfer', (5,)),
('mosi-bits', 'MOSI bits', (3,)),
+ ('mosi-data', 'MOSI data', (1,)),
+ ('mosi-transfer', 'MOSI transfer', (6,)),
('other', 'Other', (4,)),
)
binary = (
self.cs_was_deasserted = False
self.have_cs = self.have_miso = self.have_mosi = None
- def metadata(self, key, value):
- if key == srd.SRD_CONF_SAMPLERATE:
- self.samplerate = value
-
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
self.out_binary = self.register(srd.OUTPUT_BINARY)
- if self.samplerate:
- self.out_bitrate = self.register(srd.OUTPUT_META,
- meta=(int, 'Bitrate', 'Bitrate during transfers'))
+ self.out_bitrate = self.register(srd.OUTPUT_META,
+ meta=(int, 'Bitrate', 'Bitrate during transfers'))
self.bw = (self.options['wordsize'] + 7) // 8
+ def metadata(self, key, value):
+ if key == srd.SRD_CONF_SAMPLERATE:
+ self.samplerate = value
+
def putw(self, data):
self.put(self.ss_block, self.samplenum, self.out_ann, data)
self.ss_transfer = self.samplenum
self.misobytes = []
self.mosibytes = []
- else:
+ elif self.ss_transfer != -1:
+ if self.have_miso:
+ self.put(self.ss_transfer, self.samplenum, self.out_ann,
+ [5, [' '.join(format(x.val, '02X') for x in self.misobytes)]])
+ if self.have_mosi:
+ self.put(self.ss_transfer, self.samplenum, self.out_ann,
+ [6, [' '.join(format(x.val, '02X') for x in self.mosibytes)]])
self.put(self.ss_transfer, self.samplenum, self.out_python,
['TRANSFER', self.mosibytes, self.misobytes])