configure.ac: Bump libtool/library version from 1:0:0 to 2:0:0.

[libsigrokdecode.git] / decoders / spi / pd.py

diff --git a/decoders/spi/pd.py b/decoders/spi/pd.py
index 7d84b3d53c123aaff8d3ae5e12099fea6e8e5868..5bab8f75f16c4d305e08b4937deb57b1be44791f 100644 (file)
--- a/decoders/spi/pd.py
+++ b/decoders/spi/pd.py
@@ -24,14 +24,14 @@ import sigrokdecode as srd
 '''
 OUTPUT_PYTHON format:
 
-SPI packet:
-[<cmd>, <data1>, <data2>]
+Packet:
+[<ptype>, <data1>, <data2>]
 
-Commands:
+<ptype>:
  - 'DATA': <data1> contains the MISO data, <data2> contains the MOSI data.
    The data is _usually_ 8 bits (but can also be fewer or more bits).
    Both data items are Python numbers (not strings), or None if the respective
-   probe was not supplied.
+   channel was not supplied.
  - 'BITS': <data1>/<data2> contain a list of bit values in this MISO/MOSI data
    item, and for each of those also their respective start-/endsample numbers.
  - 'CS CHANGE': <data1> is the old CS# pin value, <data2> is the new value.
@@ -61,7 +61,7 @@ spi_mode = {
 }
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'spi'
     name = 'SPI'
     longname = 'Serial Peripheral Interface'
@@ -69,10 +69,10 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['spi']
-    probes = (
+    channels = (
         {'id': 'clk', 'name': 'CLK', 'desc': 'Clock'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'miso', 'name': 'MISO', 'desc': 'Master in, slave out'},
         {'id': 'mosi', 'name': 'MOSI', 'desc': 'Master out, slave in'},
         {'id': 'cs', 'name': 'CS#', 'desc': 'Chip-select'},