word <worditemcount> is 7, and so on.
'''
-def probe_list(num_probes):
+def channel_list(num_channels):
l = [{'id': 'clk', 'name': 'CLK', 'desc': 'Clock line'}]
- for i in range(num_probes):
+ for i in range(num_channels):
d = {'id': 'd%d' % i, 'name': 'D%d' % i, 'desc': 'Data line %d' % i}
l.append(d)
return tuple(l)
+class ChannelError(Exception):
+ pass
+
class Decoder(srd.Decoder):
- api_version = 1
+ api_version = 2
id = 'parallel'
name = 'Parallel'
longname = 'Parallel sync bus'
license = 'gplv2+'
inputs = ['logic']
outputs = ['parallel']
- optional_probes = probe_list(8)
+ optional_channels = channel_list(8)
options = (
{'id': 'clock_edge', 'desc': 'Clock edge to sample on',
'default': 'rising', 'values': ('rising', 'falling')},
self.oldpins = None
self.ss_item = self.es_item = None
self.first = True
- self.state = 'IDLE'
def start(self):
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.items.append(item)
self.itemcount += 1
- if self.first == True:
+ if self.first:
# Save the start sample and item for later (no output yet).
self.ss_item = self.samplenum
self.first = False
continue
self.oldpins = pins
- # State machine.
- if self.state == 'IDLE':
- if pins[0] not in (0, 1):
- self.handle_bits(pins[1:])
- else:
- self.find_clk_edge(pins[0], pins[1:])
- else:
- raise Exception('Invalid state: %s' % self.state)
+ if sum(1 for p in pins if p in (0, 1)) == 0:
+ raise ChannelError('At least one channel has to be supplied.')
+ if pins[0] not in (0, 1):
+ self.handle_bits(pins[1:])
+ else:
+ self.find_clk_edge(pins[0], pins[1:])