)
def __init__(self):
+ self.reset()
+
+ def reset(self):
self.items = []
self.itemcount = 0
self.saved_item = None
self.out_python = self.register(srd.OUTPUT_PYTHON)
self.out_ann = self.register(srd.OUTPUT_ANN)
- # Assume that the initial pin state of all pins is logic 1.
- self.initial_pins = [1] * (NUM_CHANNELS + 1)
-
def putpb(self, data):
self.put(self.ss_item, self.es_item, self.out_python, data)
if self.has_channel(i):
conds.append({i: 'e'})
while True:
- self.handle_bits(self.wait(conds[:])[1:])
+ self.handle_bits(self.wait(conds)[1:])
else:
# Sample on the rising or falling CLK edge (depends on config).
while True: