microwire: Use namedtuple for the Python output.

[libsigrokdecode.git] / decoders / microwire / pd.py

diff --git a/decoders/microwire/pd.py b/decoders/microwire/pd.py
index e64732d5ee9259f44879ff434edb08ef411a662e..e5712dbf60f2c5f235db9b20cbdc5b28887cd2ad 100644 (file)
--- a/decoders/microwire/pd.py
+++ b/decoders/microwire/pd.py
@@ -18,18 +18,19 @@
 ##
 
 import sigrokdecode as srd
+from collections import namedtuple
 
 '''
 OUTPUT_PYTHON format:
 
 Packet:
-[{'ss': bit start sample number,
+[namedtuple('ss': bit start sample number,
   'se': bit end sample number,
   'si': SI bit,
   'so': SO bit,
- }, ...]
+ ), ...]
 
-Since address and word size are variable, a list of all bits in each packet 
+Since address and word size are variable, a list of all bits in each packet
 need to be output. Since Microwire is a synchronous protocol with separate
 input and output lines (SI and SO) they are provided together, but because
 Microwire is half-duplex only the SI or SO bits will be considered at once.
@@ -37,6 +38,8 @@ To be able to annotate correctly the instructions formed by the bit, the start
 and end sample number of each bit (pair of SI/SO bit) are provided.
 '''
 
+PyPacket = namedtuple('PyPacket', 'ss se si so')
+
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'microwire'
@@ -119,16 +122,16 @@ class Decoder(srd.Decoder):
                     if len(change['matched']) > 2 and change['matched'][2]:
                         if bit_so == 0 and change['so']:
                             # Rising edge Busy -> Ready.
-                            self.put(start_samplenum, change['samplenum'], 
+                            self.put(start_samplenum, change['samplenum'],
                                      self.out_ann, [4, ['Busy', 'B']])
                         start_samplenum = change['samplenum']
                         bit_so = change['so']
                 # Put last state.
                 if bit_so == 0:
-                    self.put(start_samplenum, packet[-1]['samplenum'], 
+                    self.put(start_samplenum, packet[-1]['samplenum'],
                              self.out_ann, [4, ['Busy', 'B']])
                 else:
-                    self.put(start_samplenum, packet[-1]['samplenum'], 
+                    self.put(start_samplenum, packet[-1]['samplenum'],
                              self.out_ann, [3, ['Ready', 'R']])
             else:
                 # Bit communication.
@@ -139,7 +142,7 @@ class Decoder(srd.Decoder):
                 bit_si = 0 # SI value at rising clock edge.
                 bit_so = 0 # SO value at falling clock edge.
                 start_bit = True # Start bit incoming (first bit).
-                python_output = [] # Python output data.
+                pydata = [] # Python output data.
                 for change in packet:
                     if len(change['matched']) > 1 and change['matched'][1]:
                         # Clock edge.
@@ -167,9 +170,8 @@ class Decoder(srd.Decoder):
                                              [2, ['SO bit: %d' % bit_so,
                                                   'SO: %d' % bit_so,
                                                   '%d' % bit_so]])
-                                    python_output.append({'ss': bit_start,
-                                                 'se': change['samplenum'],
-                                                 'si': bit_si, 'so': bit_so})
+                                    pydata.append(PyPacket(bit_start,
+                                        change['samplenum'], bit_si, bit_so))
                             bit_start = change['samplenum']
                             bit_si = change['si']
                         else: # Falling clock edge.
@@ -183,9 +185,8 @@ class Decoder(srd.Decoder):
                         self.put(bit_start, change['samplenum'], self.out_ann,
                                  [2, ['SO bit: %d' % bit_so,
                                       'SO: %d' % bit_so, '%d' % bit_so]])
-                        python_output.append({'ss': bit_start,
-                                              'se': change['samplenum'],
-                                              'si': bit_si, 'so': bit_so})
+                        pydata.append(PyPacket(bit_start, change['samplenum'],
+                                      bit_si, bit_so))
                 self.put(packet[0]['samplenum'],
                          packet[len(packet) - 1]['samplenum'],
-                         self.out_python, python_output)
+                         self.out_python, pydata)