import sigrokdecode as srd
class Decoder(srd.Decoder):
- api_version = 2
+ api_version = 3
id = 'mdio'
name = 'MDIO'
longname = 'Management Data Input/Output'
)
def __init__(self):
- self.last_mdc = 1
+ self.reset()
+
+ def reset(self):
self.illegal_bus = 0
self.samplenum = -1
self.clause45_addr = -1 # Clause 45 is context sensitive.
if self.options['show_debug_bits'] == 'yes':
self.put(ss, es, self.out_ann, [1, ['%d' % (self.bitcount - 1), '%d' % ((self.bitcount - 1) % 10)]])
+ def putff(self, data):
+ self.put(self.ss_frame_field, self.samplenum, self.out_ann, data)
+
def putdata(self):
self.put(self.ss_frame_field, self.mdiobits[0][2], self.out_ann,
[2, ['DATA: %04X' % self.data, 'DATA', 'D']])
st = ['ST (Clause 45)', 'ST 45']
else:
st = ['ST (Clause 22)', 'ST 22']
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [2, st + ['ST', 'S']])
+ self.putff([2, st + ['ST', 'S']])
self.ss_frame_field = self.samplenum
if mdio:
op = ['OP: READ', 'OP: R']
else:
op = ['OP: READ', 'OP: R'] if self.opcode else ['OP: WRITE', 'OP: W']
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [2, op + ['OP', 'O']])
+ self.putff([2, op + ['OP', 'O']])
if self.op_invalid:
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [4, ['OP %s' % self.op_invalid, 'OP', 'O']])
+ self.putff([4, ['OP %s' % self.op_invalid, 'OP', 'O']])
self.ss_frame_field = self.samplenum
self.portad_bits -= 1
self.portad |= mdio << self.portad_bits
prtad = ['PRTAD: %02d' % self.portad, 'PRT', 'P']
else:
prtad = ['PHYAD: %02d' % self.portad, 'PHY', 'P']
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [2, prtad])
+ self.putff([2, prtad])
self.ss_frame_field = self.samplenum
self.devad_bits -= 1
self.devad |= mdio << self.devad_bits
regad = ['DEVAD: %02d' % self.devad, 'DEV', 'D']
else:
regad = ['REGAD: %02d' % self.devad, 'REG', 'R']
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [2, regad])
+ self.putff([2, regad])
self.ss_frame_field = self.samplenum
if mdio != 1 and ((self.clause45 and self.opcode < 2)
or (not self.clause45 and self.opcode == 0)):
def state_DATA(self, mdio):
if self.data == -1:
self.data = 0
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [2, ['TA', 'T']])
+ self.putff([2, ['TURNAROUND', 'TA', 'T']])
if self.ta_invalid:
- self.put(self.ss_frame_field, self.samplenum, self.out_ann,
- [4, ['TA%s' % self.ta_invalid, 'TA', 'T']])
+ self.putff([4, ['TURNAROUND%s' % self.ta_invalid,
+ 'TA%s' % self.ta_invalid, 'TA', 'T']])
self.ss_frame_field = self.samplenum
self.data_bits -= 1
self.data |= mdio << self.data_bits
self.process_state(self.state, mdio)
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
- # Ignore identical samples early on (for performance reasons).
- if self.last_mdc == pins[0]:
- continue
- self.last_mdc = pins[0]
- if pins[0] == 0: # Check for rising edge.
- continue
-
- # Found the correct clock edge, now get/handle the bit(s).
+ def decode(self):
+ while True:
+ # Process pin state upon rising MDC edge.
+ pins = self.wait({0: 'r'})
self.handle_bit(pins[1])