import sigrokdecode as srd
class Decoder(srd.Decoder):
- api_version = 2
+ api_version = 3
id = 'mdio'
name = 'MDIO'
longname = 'Management Data Input/Output'
- desc = 'Half-duplex sync serial bus for MII management between MAC and PHY.'
+ desc = 'MII management bus between MAC and PHY.'
license = 'bsd'
inputs = ['logic']
outputs = ['mdio']
+ tags = ['Networking']
channels = (
{'id': 'mdc', 'name': 'MDC', 'desc': 'Clock'},
{'id': 'mdio', 'name': 'MDIO', 'desc': 'Data'},
)
def __init__(self):
- self.last_mdc = 1
+ self.reset()
+
+ def reset(self):
self.illegal_bus = 0
self.samplenum = -1
self.clause45_addr = -1 # Clause 45 is context sensitive.
if self.clause45 and self.clause45_addr != -1:
decoded_min += str.format('ADDR: %04X ' % self.clause45_addr)
elif self.clause45:
- decoded_min += str.format('ADDR: UKWN ' % self.clause45_addr)
+ decoded_min += str.format('ADDR: UKWN ')
if self.clause45 and self.opcode > 1 \
or (not self.clause45 and self.opcode):
self.process_state(self.state, mdio)
- def decode(self, ss, es, data):
- for (self.samplenum, pins) in data:
- # Ignore identical samples early on (for performance reasons).
- if self.last_mdc == pins[0]:
- continue
- self.last_mdc = pins[0]
- if pins[0] == 0: # Check for rising edge.
- continue
-
- # Found the correct clock edge, now get/handle the bit(s).
+ def decode(self):
+ while True:
+ # Process pin state upon rising MDC edge.
+ pins = self.wait({0: 'r'})
self.handle_bit(pins[1])