spiflash: Handle CS# transitions, allow variable-length transfers

[libsigrokdecode.git] / decoders / lpc / pd.py

diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py
index b626e0d338e67192103dcc63e6462a89ca85f9c5..936839442346a5b609d87c11b88347a2c6798205 100644 (file)
--- a/decoders/lpc/pd.py
+++ b/decoders/lpc/pd.py
@@ -136,7 +136,7 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (0,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.state = 'IDLE'
         self.oldlclk = -1
         self.samplenum = 0
@@ -346,7 +346,7 @@ class Decoder(srd.Decoder):
             if self.state == 'IDLE':
                 # A valid LPC cycle starts with LFRAME# being asserted (low).
                 if lframe != 0:
-                   continue
+                    continue
                 self.ss_block = self.samplenum
                 self.state = 'GET START'
                 self.lad = -1
@@ -365,4 +365,3 @@ class Decoder(srd.Decoder):
                 self.handle_get_data(lad, lad_bits)
             elif self.state == 'GET TAR2':
                 self.handle_get_tar2(lad, lad_bits)
-