uart: Fix code comment.

[libsigrokdecode.git] / decoders / lpc / pd.py

diff --git a/decoders/lpc/pd.py b/decoders/lpc/pd.py
index 2a127107b3034614df9ca6d67950f960eeab9a8b..5e25db4779ba886070fecd752ecf848926eec966 100644 (file)
--- a/decoders/lpc/pd.py
+++ b/decoders/lpc/pd.py
@@ -96,7 +96,7 @@ fields = {
 }
 
 class Decoder(srd.Decoder):
-    api_version = 1
+    api_version = 2
     id = 'lpc'
     name = 'LPC'
     longname = 'Low-Pin-Count'
@@ -104,7 +104,7 @@ class Decoder(srd.Decoder):
     license = 'gplv2+'
     inputs = ['logic']
     outputs = ['lpc']
-    probes = (
+    channels = (
         {'id': 'lframe', 'name': 'LFRAME#', 'desc': 'Frame'},
         {'id': 'lclk',   'name': 'LCLK',    'desc': 'Clock'},
         {'id': 'lad0',   'name': 'LAD[0]',  'desc': 'Addr/control/data 0'},
@@ -112,7 +112,7 @@ class Decoder(srd.Decoder):
         {'id': 'lad2',   'name': 'LAD[2]',  'desc': 'Addr/control/data 2'},
         {'id': 'lad3',   'name': 'LAD[3]',  'desc': 'Addr/control/data 3'},
     )
-    optional_probes = (
+    optional_channels = (
         {'id': 'lreset', 'name': 'LRESET#', 'desc': 'Reset'},
         {'id': 'ldrq',   'name': 'LDRQ#',   'desc': 'Encoded DMA / bus master request'},
         {'id': 'serirq', 'name': 'SERIRQ',  'desc': 'Serialized IRQ'},
@@ -152,7 +152,6 @@ class Decoder(srd.Decoder):
         self.ss_block = self.es_block = None
 
     def start(self):
-        # self.out_python = self.register(srd.OUTPUT_PYTHON)
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
     def putb(self, data):
@@ -347,7 +346,7 @@ class Decoder(srd.Decoder):
             if self.state == 'IDLE':
                 # A valid LPC cycle starts with LFRAME# being asserted (low).
                 if lframe != 0:
-                   continue
+                    continue
                 self.ss_block = self.samplenum
                 self.state = 'GET START'
                 self.lad = -1
@@ -366,6 +365,3 @@ class Decoder(srd.Decoder):
                 self.handle_get_data(lad, lad_bits)
             elif self.state == 'GET TAR2':
                 self.handle_get_tar2(lad, lad_bits)
-            else:
-                raise Exception('Invalid state: %s' % self.state)
-