# 'signals': [{'SCL': }]}
#
+import sigrokdecode
+
+# symbols for i2c decoders up the stack
+START = 1
+START_REPEAT = 2
+STOP = 3
+ACK = 4
+NACK = 5
+ADDRESS_READ = 6
+ADDRESS_WRITE = 7
+DATA_READ = 8
+DATA_WRITE = 9
+
# States
FIND_START = 0
FIND_ADDRESS = 1
FIND_DATA = 2
-class Sample():
- def __init__(self, data):
- self.data = data
- def probe(self, probe):
- s = ord(self.data[probe / 8]) & (1 << (probe % 8))
- return True if s else False
-
-def sampleiter(data, unitsize):
- for i in range(0, len(data), unitsize):
- yield(Sample(data[i:i+unitsize]))
-class Decoder():
+class Decoder(sigrokdecode.Decoder):
id = 'i2c'
name = 'I2C'
longname = 'Inter-Integrated Circuit (I2C) bus'
license = 'gplv2+'
inputs = ['logic']
outputs = ['i2c']
- probes = {
- 'scl': {'ch': 0, 'name': 'SCL', 'desc': 'Serial clock line'},
- 'sda': {'ch': 1, 'name': 'SDA', 'desc': 'Serial data line'},
- }
+ probes = [
+ {'id': 'scl', 'name': 'SCL', 'desc': 'Serial clock line'},
+ {'id': 'sda', 'name': 'SDA', 'desc': 'Serial data line'},
+ ]
options = {
'address-space': ['Address space (in bits)', 7],
}
def __init__(self, **kwargs):
- self.probes = Decoder.probes.copy()
-
- # TODO: Don't hardcode the number of channels.
- self.channels = 8
-
- self.samplenum = 0
+ self.output_protocol = None
+ self.output_annotation = None
+ self.samplecnt = 0
self.bitcount = 0
self.databyte = 0
self.wr = -1
self.startsample = -1
self.is_repeat_start = 0
-
self.state = FIND_START
-
- # Get the channel/probe number of the SCL/SDA signals.
- self.scl_bit = self.probes['scl']['ch']
- self.sda_bit = self.probes['sda']['ch']
-
self.oldscl = None
self.oldsda = None
def start(self, metadata):
- self.unitsize = metadata["unitsize"]
+ self.output_protocol = self.output_new(2)
+ self.output_annotation = self.output_new(1)
def report(self):
pass
return True
return False
- def find_start(self, scl, sda):
- out = []
- # o = {'type': 'S', 'range': (self.samplenum, self.samplenum),
- # 'data': None, 'ann': None},
- o = (self.is_repeat_start == 1) and 'Sr' or 'S'
- out.append(o)
+ def found_start(self, scl, sda):
+ if self.is_repeat_start == 1:
+ out_proto = [ START_REPEAT ]
+ out_ann = [ "START REPEAT" ]
+ else:
+ out_proto = [ START ]
+ out_ann = [ "START" ]
+ self.put(self.output_protocol, out_proto)
+ self.put(self.output_annotation, out_ann)
+
self.state = FIND_ADDRESS
self.bitcount = self.databyte = 0
self.is_repeat_start = 1
self.wr = -1
- return out
- def find_address_or_data(self, scl, sda):
+ def found_address_or_data(self, scl, sda):
"""Gather 8 bits of data plus the ACK/NACK bit."""
- out = o = []
if self.startsample == -1:
- self.startsample = self.samplenum
+ # TODO: should be samplenum, as received from the feed
+ self.startsample = self.samplecnt
self.bitcount += 1
# Address and data are transmitted MSB-first.
# We received 8 address/data bits and the ACK/NACK bit.
self.databyte >>= 1 # Shift out unwanted ACK/NACK bit here.
- ack = (sda == 1) and 'N' or 'A'
-
if self.state == FIND_ADDRESS:
d = self.databyte & 0xfe
# The READ/WRITE bit is only in address bytes, not data bytes.
- self.wr = (self.databyte & 1) and 1 or 0
+ self.wr = 1 if (self.databyte & 1) else 0
elif self.state == FIND_DATA:
d = self.databyte
else:
# TODO: Error?
pass
- # o = {'type': self.state,
- # 'range': (self.startsample, self.samplenum - 1),
- # 'data': d, 'ann': None}
-
- o = {'data': '0x%02x' % d}
-
+ out_proto = []
+ out_ann = []
# TODO: Simplify.
if self.state == FIND_ADDRESS and self.wr == 1:
- o['type'] = 'AW'
+ cmd = ADDRESS_WRITE
+ ann = 'ADDRESS WRITE'
elif self.state == FIND_ADDRESS and self.wr == 0:
- o['type'] = 'AR'
+ cmd = ADDRESS_READ
+ ann = 'ADDRESS READ'
elif self.state == FIND_DATA and self.wr == 1:
- o['type'] = 'DW'
+ cmd = DATA_WRITE
+ ann = 'DATA WRITE'
elif self.state == FIND_DATA and self.wr == 0:
- o['type'] = 'DR'
+ cmd = DATA_READ
+ ann = 'DATA READ'
+ out_proto.append( [cmd, d] )
+ out_ann.append( ["%s" % ann, "0x%02x" % d] )
+
+ if sda == 1:
+ out_proto.append( [NACK] )
+ out_ann.append( ["NACK"] )
+ else:
+ out_proto.append( [ACK] )
+ out_ann.append( ["ACK"] )
- out.append(o)
+ self.put(self.output_protocol, out_proto)
+ self.put(self.output_annotation, out_ann)
- # o = {'type': ack, 'range': (self.samplenum, self.samplenum),
- # 'data': None, 'ann': None}
- o = ack
- out.append(o)
self.bitcount = self.databyte = 0
self.startsample = -1
# So, either find a STOP condition or another data byte next.
pass
- return out
-
- def find_stop(self, scl, sda):
- out = o = []
+ def found_stop(self, scl, sda):
+ self.put(self.output_protocol, [ STOP ])
+ self.put(self.output_annotation, [ "STOP" ])
- # o = {'type': 'P', 'range': (self.samplenum, self.samplenum),
- # 'data': None, 'ann': None},
- o = 'P'
- out.append(o)
self.state = FIND_START
self.is_repeat_start = 0
self.wr = -1
- return out
-
- def decode(self, data):
- """I2C protocol decoder"""
-
- out = []
- o = ack = d = ''
-
- # We should accept a list of samples and iterate...
- for sample in sampleiter(data['data'], self.unitsize):
+ def put(self, output_id, data):
+ # inject sample range into the call up to sigrok
+ super(Decoder, self).put(0, 0, output_id, data)
- # TODO: Eliminate the need for ord().
- s = ord(sample.data)
-
- # TODO: Start counting at 0 or 1?
- self.samplenum += 1
+ def decode(self, timeoffset, duration, data):
+ for samplenum, (scl, sda) in data:
+ self.samplecnt += 1
# First sample: Save SCL/SDA value.
if self.oldscl == None:
- # Get SCL/SDA bit values (0/1 for low/high) of the first sample.
- self.oldscl = (s & (1 << self.scl_bit)) >> self.scl_bit
- self.oldsda = (s & (1 << self.sda_bit)) >> self.sda_bit
+ self.oldscl = scl
+ self.oldsda = sda
continue
- # Get SCL/SDA bit values (0/1 for low/high).
- scl = (s & (1 << self.scl_bit)) >> self.scl_bit
- sda = (s & (1 << self.sda_bit)) >> self.sda_bit
-
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# State machine.
if self.state == FIND_START:
if self.is_start_condition(scl, sda):
- out += self.find_start(scl, sda)
+ self.found_start(scl, sda)
elif self.state == FIND_ADDRESS:
if self.is_data_bit(scl, sda):
- out += self.find_address_or_data(scl, sda)
+ self.found_address_or_data(scl, sda)
elif self.state == FIND_DATA:
if self.is_data_bit(scl, sda):
- out += self.find_address_or_data(scl, sda)
+ self.found_address_or_data(scl, sda)
elif self.is_start_condition(scl, sda):
- out += self.find_start(scl, sda)
+ self.found_start(scl, sda)
elif self.is_stop_condition(scl, sda):
- out += self.find_stop(scl, sda)
+ self.found_stop(scl, sda)
else:
# TODO: Error?
pass
self.oldscl = scl
self.oldsda = sda
- if out != []:
- sigrok.put(out)
-
-import sigrok
-
-sigrok.register(Decoder)
-
projects / libsigrokdecode.git / blobdiff