##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
##
## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
##
self.wr = -1
self.is_repeat_start = 0
self.state = 'FIND START'
- self.oldscl = None
- self.oldsda = None
- self.oldpins = None
+ self.oldscl = 1
+ self.oldsda = 1
+ self.oldpins = (1, 1)
def start(self, metadata):
self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
continue
self.oldpins, (scl, sda) = pins, pins
- # First sample: Save SCL/SDA value.
- if self.oldscl == None:
- self.oldscl = scl
- self.oldsda = sda
- continue
-
# TODO: Wait until the bus is idle (SDA = SCL = 1) first?
# State machine.
if self.is_data_bit(scl, sda):
self.get_ack(scl, sda)
else:
- raise Exception('Invalid state %d' % self.STATE)
+ raise Exception('Invalid state: %s' % self.state)
# Save current SDA/SCL values for the next round.
self.oldscl = scl