uart: Output data in separate RX and TX annotation types.

[libsigrokdecode.git] / decoders / i2c / pd.py

diff --git a/decoders/i2c/pd.py b/decoders/i2c/pd.py
index 40baf44e572e47f7fe8b1c5db66fdcec93da5d99..c2eb5246fccb332f6bd81c6f71effc0cd8dc07a4 100644 (file)
--- a/decoders/i2c/pd.py
+++ b/decoders/i2c/pd.py
@@ -1,5 +1,5 @@
 ##
-## This file is part of the sigrok project.
+## This file is part of the libsigrokdecode project.
 ##
 ## Copyright (C) 2010-2011 Uwe Hermann <uwe@hermann-uwe.de>
 ##
@@ -86,9 +86,9 @@ class Decoder(srd.Decoder):
         self.wr = -1
         self.is_repeat_start = 0
         self.state = 'FIND START'
-        self.oldscl = None
-        self.oldsda = None
-        self.oldpins = None
+        self.oldscl = 1
+        self.oldsda = 1
+        self.oldpins = (1, 1)
 
     def start(self, metadata):
         self.out_proto = self.add(srd.OUTPUT_PROTO, 'i2c')
@@ -206,12 +206,6 @@ class Decoder(srd.Decoder):
                 continue
             self.oldpins, (scl, sda) = pins, pins
 
-            # First sample: Save SCL/SDA value.
-            if self.oldscl == None:
-                self.oldscl = scl
-                self.oldsda = sda
-                continue
-
             # TODO: Wait until the bus is idle (SDA = SCL = 1) first?
 
             # State machine.