cjtag: Use += operator where possible.

[libsigrokdecode.git] / decoders / ds1307 / pd.py

diff --git a/decoders/ds1307/pd.py b/decoders/ds1307/pd.py
index 556d5930c30327c9c43f02756049ff63e28f6138..c6a2e342f3360e626631767a201ec7af13b42369 100644 (file)
--- a/decoders/ds1307/pd.py
+++ b/decoders/ds1307/pd.py
@@ -59,14 +59,14 @@ class Decoder(srd.Decoder):
     desc = 'Dallas DS1307 realtime clock module protocol.'
     license = 'gplv2+'
     inputs = ['i2c']
-    outputs = ['ds1307']
+    outputs = []
     tags = ['Clock/timing', 'IC']
     annotations =  regs_and_bits() + (
         ('read-datetime', 'Read date/time'),
         ('write-datetime', 'Write date/time'),
         ('reg-read', 'Register read'),
         ('reg-write', 'Register write'),
-        ('warnings', 'Warnings'),
+        ('warning', 'Warning'),
     )
     annotation_rows = (
         ('bits', 'Bits', tuple(range(9, 24))),