modbus: Add missing annotation class names.

[libsigrokdecode.git] / decoders / dmx512 / pd.py

diff --git a/decoders/dmx512/pd.py b/decoders/dmx512/pd.py
index 4da7076f10be36aa959de33a81ebcdc35e85e160..9ef82d78180f275e35500a632981c08db495cfdb 100644 (file)
--- a/decoders/dmx512/pd.py
+++ b/decoders/dmx512/pd.py
@@ -24,10 +24,11 @@ class Decoder(srd.Decoder):
     id = 'dmx512'
     name = 'DMX512'
     longname = 'Digital MultipleX 512'
-    desc = 'Professional lighting control protocol.'
+    desc = 'Digital MultipleX 512 (DMX512) lighting protocol.'
     license = 'gplv2+'
     inputs = ['logic']
-    outputs = ['dmx512']
+    outputs = []
+    tags = ['Embedded/industrial', 'Lighting']
     channels = (
         {'id': 'dmx', 'name': 'DMX data', 'desc': 'Any DMX data line'},
     )
@@ -36,7 +37,7 @@ class Decoder(srd.Decoder):
         ('break', 'Break'),
         ('mab', 'Mark after break'),
         ('startbit', 'Start bit'),
-        ('stopbits', 'Stop bit'),
+        ('stopbit', 'Stop bit'),
         ('startcode', 'Start code'),
         ('channel', 'Channel'),
         ('interframe', 'Interframe'),
@@ -45,13 +46,16 @@ class Decoder(srd.Decoder):
         ('error', 'Error'),
     )
     annotation_rows = (
-        ('name', 'Logical', (1, 2, 5, 6, 7, 8)),
-        ('data', 'Data', (9,)),
         ('bits', 'Bits', (0, 3, 4)),
+        ('data-vals', 'Data', (9,)),
+        ('logical-vals', 'Logical', (1, 2, 5, 6, 7, 8)),
         ('errors', 'Errors', (10,)),
     )
 
     def __init__(self):
+        self.reset()
+
+    def reset(self):
         self.samplerate = None
         self.sample_usec = None
         self.run_start = -1
@@ -101,7 +105,7 @@ class Decoder(srd.Decoder):
             # Mark and read a single transmitted byte
             # (start bit, 8 data bits, 2 stop bits).
             elif self.state == 'READ BYTE':
-                (dmx,) = self.wait({'skip': 1})
+                (dmx,) = self.wait()
                 self.next_sample = self.run_start + (self.bit + 1) * self.skip_per_bit
                 self.aggreg += dmx
                 if self.samplenum != self.next_sample: