spiflash: Handle CS# transitions, allow variable-length transfers

[libsigrokdecode.git] / decoders / dcf77 / pd.py

diff --git a/decoders/dcf77/pd.py b/decoders/dcf77/pd.py
index 14d8637ff00fa287a928e38c18319e96c80c0dd2..0f1d3d1910cf2dddba62f29395451448a4c9dc26 100644 (file)
--- a/decoders/dcf77/pd.py
+++ b/decoders/dcf77/pd.py
@@ -20,10 +20,7 @@
 
 import sigrokdecode as srd
 import calendar
-
-# Return the specified BCD number (max. 8 bits) as integer.
-def bcd2int(b):
-    return (b & 0x0f) + ((b >> 4) * 10)
+from common.srdhelper import bcd2int
 
 class SamplerateError(Exception):
     pass
@@ -68,7 +65,7 @@ class Decoder(srd.Decoder):
         ('warnings', 'Warnings', (19,)),
     )
 
-    def __init__(self, **kwargs):
+    def __init__(self):
         self.samplerate = None
         self.state = 'WAIT FOR RISING EDGE'
         self.oldpins = None
@@ -242,7 +239,7 @@ class Decoder(srd.Decoder):
             # Even parity over date bits (36-58): DCF77 bit 58.
             parity = self.datebits.count(1)
             s = 'OK' if ((parity % 2) == 0) else 'INVALID!'
-            self.putx([16, ['Date parity: %s' % s, 'DP: %s' %s]])
+            self.putx([16, ['Date parity: %s' % s, 'DP: %s' % s]])
             self.datebits = []
         else:
             raise Exception('Invalid DCF77 bit: %d' % c)
@@ -314,4 +311,3 @@ class Decoder(srd.Decoder):
                 self.state = 'WAIT FOR RISING EDGE'
 
             self.oldval = val
-