nrf905: Simplify a few code snippets.

[libsigrokdecode.git] / decoders / adxl345 / pd.py

diff --git a/decoders/adxl345/pd.py b/decoders/adxl345/pd.py
index 8b231474879d684f3ec9614019c23c5c9124977c..2d53e4c0d17bf249658098feddecd918404243af 100644 (file)
--- a/decoders/adxl345/pd.py
+++ b/decoders/adxl345/pd.py
@@ -60,6 +60,8 @@ class Bit():
 
 Ann = SrdIntEnum.from_str('Ann', 'READ WRITE MB REG_ADDRESS REG_DATA WARNING')
 
+St = SrdIntEnum.from_str('St', 'IDLE ADDRESS_BYTE DATA')
+
 class Decoder(srd.Decoder):
     api_version = 3
     id = 'adxl345'
@@ -92,7 +94,7 @@ class Decoder(srd.Decoder):
         self.operation = None
         self.address = 0
         self.data = -1
-        self.state = 'IDLE'
+        self.state = St.IDLE
         self.ss, self.es = -1, -1
         self.samples_per_bit = 0
 
@@ -158,37 +160,36 @@ class Decoder(srd.Decoder):
         else:
             self.putx([Ann.REG_DATA, [str(data)]])
 
-    def handle_reg_0x1D(self, data):
+    def handle_reg_0x1d(self, data):
         self.handle_reg_with_scaling_factor(data, 62.5, 'Threshold', 'g',
             error_messages['undesirable'])
 
-    def handle_reg_0x1E(self, data):
+    def handle_reg_0x1e(self, data):
         self.handle_reg_with_scaling_factor(data, 15.6, 'OFSX', 'g', None)
 
-    def handle_reg_0x1F(self, data):
+    def handle_reg_0x1f(self, data):
         self.handle_reg_with_scaling_factor(data, 15.6, 'OFSY', 'g', None)
 
     def handle_reg_0x20(self, data):
         self.handle_reg_with_scaling_factor(data, 15.6, 'OFSZ', 'g', None)
 
     def handle_reg_0x21(self, data):
-        self.handle_reg_with_scaling_factor(data, 0.625, 'Time', 's',
+        self.handle_reg_with_scaling_factor(data, 0.625, 'Duration', 's',
             error_messages['dis_single_double'])
 
     def handle_reg_0x22(self, data):
-        self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
+        self.handle_reg_with_scaling_factor(data, 1.25, 'Latency', 's',
             error_messages['dis_double'])
 
     def handle_reg_0x23(self, data):
-        self.handle_reg_with_scaling_factor(data, 1.25, 'Latent', 's',
+        self.handle_reg_with_scaling_factor(data, 1.25, 'Window', 's',
             error_messages['dis_double'])
 
     def handle_reg_0x24(self, data):
-        self.handle_reg_with_scaling_factor(data, 62.5, 'Latent', 's',
-            error_messages['undesirable'])
+        self.handle_reg_0x1d(data)
 
     def handle_reg_0x25(self, data):
-        self.handle_reg_0x1D(data)
+        self.handle_reg_0x1d(data)
 
     def handle_reg_0x26(self, data):
         self.handle_reg_with_scaling_factor(data, 1000, 'Time', 's',
@@ -206,13 +207,13 @@ class Decoder(srd.Decoder):
         self.interpret_bits(data, bits)
 
     def handle_reg_0x28(self, data):
-        self.handle_reg_0x1D(data)
+        self.handle_reg_0x1d(data)
 
     def handle_reg_0x29(self, data):
         self.handle_reg_with_scaling_factor(data, 5, 'Time', 's',
             error_messages['undesirable'])
 
-    def handle_reg_0x2A(self, data):
+    def handle_reg_0x2a(self, data):
         bits = [Bit('', BitType.UNUSED),
                 Bit('', BitType.UNUSED),
                 Bit('', BitType.UNUSED),
@@ -224,7 +225,7 @@ class Decoder(srd.Decoder):
                 Bit('TAP_Z', BitType.ENABLE)]
         self.interpret_bits(data, bits)
 
-    def handle_reg_0x2B(self, data):
+    def handle_reg_0x2b(self, data):
         bits = [Bit('', BitType.UNUSED),
                 Bit('ACT_X', BitType.SOURCE),
                 Bit('ACT_Y', BitType.SOURCE),
@@ -236,7 +237,7 @@ class Decoder(srd.Decoder):
                 Bit('TAP_Z', BitType.SOURCE)]
         self.interpret_bits(data, bits)
 
-    def handle_reg_0x2C(self, data):
+    def handle_reg_0x2c(self, data):
         bits = [Bit('', BitType.UNUSED),
                 Bit('', BitType.UNUSED),
                 Bit('', BitType.UNUSED),
@@ -244,10 +245,10 @@ class Decoder(srd.Decoder):
         bits_values = self.interpret_bits(data, bits)
 
         start_index, stop_index = 0, 3
-        rate = self.get_decimal_number(bits_values, start_index, start_index)
+        rate = self.get_decimal_number(bits_values, start_index, stop_index)
         self.putbs([Ann.REG_DATA, ['%f' % rate_code[rate]]], stop_index, start_index)
 
-    def handle_reg_0x2D(self, data):
+    def handle_reg_0x2d(self, data):
         bits = [Bit('', BitType.UNUSED),
                 Bit('', BitType.UNUSED),
                 Bit('', BitType.OTHER, {1: ['Link'], 0: ['Unlink'], }),
@@ -261,7 +262,7 @@ class Decoder(srd.Decoder):
         frequency = 2 ** (~wakeup & 0x03)
         self.putbs([Ann.REG_DATA, ['%d Hz' % frequency]], stop_index, start_index)
 
-    def handle_reg_0x2E(self, data):
+    def handle_reg_0x2e(self, data):
         bits = [Bit('DATA_READY', BitType.ENABLE),
                 Bit('SINGLE_TAP', BitType.ENABLE),
                 Bit('DOUBLE_TAP', BitType.ENABLE),
@@ -272,7 +273,7 @@ class Decoder(srd.Decoder):
                 Bit('Overrun', BitType.ENABLE)]
         self.interpret_bits(data, bits)
 
-    def handle_reg_0x2F(self, data):
+    def handle_reg_0x2f(self, data):
         bits = [Bit('DATA_READY', BitType.INTERRUPT),
                 Bit('SINGLE_TAP', BitType.INTERRUPT),
                 Bit('DOUBLE_TAP', BitType.INTERRUPT),
@@ -376,9 +377,9 @@ class Decoder(srd.Decoder):
             cs_old, cs_new = data[1:]
             if cs_old is not None and cs_old == 1 and cs_new == 0:
                 self.ss, self.es = ss, es
-                self.state = 'ADDRESS-BYTE'
+                self.state = St.ADDRESS_BYTE
             else:
-                self.state = 'IDLE'
+                self.state = St.IDLE
 
         elif ptype == 'BITS':
             if data[1] is not None:
@@ -389,7 +390,7 @@ class Decoder(srd.Decoder):
             if self.mosi is None and self.miso is None:
                 return
 
-            if self.state == 'ADDRESS-BYTE':
+            if self.state == St.ADDRESS_BYTE:
                 # OPERATION BIT
                 op_bit = self.get_bit(Channel.MOSI)
                 self.put(op_bit[1], op_bit[2], self.out_ann,
@@ -412,9 +413,9 @@ class Decoder(srd.Decoder):
                     [Ann.REG_ADDRESS, ['ADDRESS: 0x%02X' % self.address, 'ADDR: 0x%02X'
                     % self.address, '0x%02X' % self.address]])
                 self.ss = -1
-                self.state = 'DATA'
+                self.state = St.DATA
 
-            elif self.state == 'DATA':
+            elif self.state == St.DATA:
                 self.reg.extend(self.mosi if self.operation == Operation.WRITE else self.miso)
 
                 self.mosi, self.miso = [], []
@@ -444,7 +445,7 @@ class Decoder(srd.Decoder):
                         self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_DATA, [str(reg_value)]])
                     else:
                         self.put(self.ss, reg_bit[2], self.out_ann, [Ann.REG_ADDRESS, registers[self.address]])
-                        handle_reg = getattr(self, 'handle_reg_0x%02X' % self.address)
+                        handle_reg = getattr(self, 'handle_reg_0x%02x' % self.address)
                         handle_reg(reg_value)
 
                     self.reg = []