adf435x: rework emission of annotations

[libsigrokdecode.git] / decoders / adf435x / pd.py

diff --git a/decoders/adf435x/pd.py b/decoders/adf435x/pd.py
index 8c31648b873707d929a4fd01b26b078c364b2851..d234a815f4f2e7fb299130cf5809e2351b91d09b 100644 (file)
--- a/decoders/adf435x/pd.py
+++ b/decoders/adf435x/pd.py
@@ -118,6 +118,9 @@ class Decoder(srd.Decoder):
     def start(self):
         self.out_ann = self.register(srd.OUTPUT_ANN)
 
+    def putg(self, ss, es, cls, data):
+        self.put(ss, es, self.out_ann, [ cls, data, ])
+
     def decode_bits(self, offset, width):
         bits = self.bits[offset:][:width]
         ss, es = bits[-1][1], bits[0][2]
@@ -125,9 +128,10 @@ class Decoder(srd.Decoder):
         return ( value, ( ss, es, ))
 
     def decode_field(self, name, offset, width, parser):
-        val, pos = self.decode_bits(offset, width)
-        self.put(pos[0], pos[1], self.out_ann, [ANN_REG,
-            ['%s: %s' % (name, parser(val) if parser else str(val))]])
+        val, ( ss, es, ) = self.decode_bits(offset, width)
+        val = parser(val) if parser else str(val)
+        text = ['%s: %s' % (name, val)]
+        self.putg(ss, es, ANN_REG, text)
         return val
 
     def decode(self, ss, es, data):
@@ -135,19 +139,33 @@ class Decoder(srd.Decoder):
 
         if ptype == 'TRANSFER':
             if len(self.bits) == 32:
-                reg_value, reg_pos = self.decode_bits(0, 3)
-                self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
-                    ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
-                     '[%d]' % reg_value]])
+                self.bits.reverse()
+                reg_value, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
+                text = [
+                    'Register: %d' % reg_value,
+                    'Reg: %d' % reg_value,
+                    '[%d]' % reg_value,
+                ]
+                self.putg(reg_ss, reg_es, ANN_REG, text)
                 if reg_value < len(regs):
                     field_descs = regs[reg_value]
                     for field_desc in field_descs:
                         field = self.decode_field(*field_desc)
             else:
-                error = "Frame error: Wrong number of bits: got %d expected 32" % len(self.bits)
-                self.put(ss, es, self.out_ann, [ANN_WARN, [error, 'Frame error']])
-            self.bits = []
+                text = [
+                    'Frame error: Bit count: want 32, got %d' % len(self.bits),
+                    'Frame error: Bit count',
+                    'Frame error',
+                ]
+                self.putg(ss, es, ANN_WARN, text)
+            self.bits.clear()
 
         if ptype == 'BITS':
             _, mosi_bits, miso_bits = data
-            self.bits = mosi_bits + self.bits
+            # Cope with the lower layer SPI decoder's output convention:
+            # Regardless of wire transfer's frame format, .decode() input
+            # provides BITS in the LE order. Accumulate in MSB order here,
+            # and reverse before data processing when 'TRANSFER' is seen.
+            mosi_bits = mosi_bits.copy()
+            mosi_bits.reverse()
+            self.bits.extend(mosi_bits)