##
import sigrokdecode as srd
+from common.srdhelper import bitpack_lsb
def disabled_enabled(v):
return ['Disabled', 'Enabled'][v]
}
ANN_REG = 0
+ANN_WARN = 1
class Decoder(srd.Decoder):
api_version = 3
annotations = (
# Sent from the host to the chip.
('write', 'Register write'),
+ ('warning', "Warnings"),
)
annotation_rows = (
('writes', 'Register writes', (ANN_REG,)),
+ ('warnings', 'Warnings', (ANN_WARN,)),
)
def __init__(self):
def start(self):
self.out_ann = self.register(srd.OUTPUT_ANN)
+ def putg(self, ss, es, cls, data):
+ self.put(ss, es, self.out_ann, [ cls, data, ])
+
def decode_bits(self, offset, width):
- return (sum([(1 << i) if self.bits[offset + i][0] else 0 for i in range(width)]),
- (self.bits[offset + width - 1][1], self.bits[offset][2]))
+ bits = self.bits[offset:][:width]
+ ss, es = bits[-1][1], bits[0][2]
+ value = bitpack_lsb(bits, 0)
+ return ( value, ( ss, es, ))
def decode_field(self, name, offset, width, parser):
- val, pos = self.decode_bits(offset, width)
- self.put(pos[0], pos[1], self.out_ann, [ANN_REG,
- ['%s: %s' % (name, parser(val) if parser else str(val))]])
+ val, ( ss, es, ) = self.decode_bits(offset, width)
+ val = parser(val) if parser else str(val)
+ text = ['%s: %s' % (name, val)]
+ self.putg(ss, es, ANN_REG, text)
return val
def decode(self, ss, es, data):
-
ptype, _, _ = data
- if ptype == 'CS-CHANGE':
- _, cs_before, cs_after = data
- if cs_before == 1:
- if len(self.bits) == 32:
- reg_value, reg_pos = self.decode_bits(0, 3)
- self.put(reg_pos[0], reg_pos[1], self.out_ann, [ANN_REG,
- ['Register: %d' % reg_value, 'Reg: %d' % reg_value,
- '[%d]' % reg_value]])
- if reg_value < len(regs):
- field_descs = regs[reg_value]
- for field_desc in field_descs:
- field = self.decode_field(*field_desc)
- self.bits = []
+ if ptype == 'TRANSFER':
+ if len(self.bits) == 32:
+ self.bits.reverse()
+ reg_value, ( reg_ss, reg_es, ) = self.decode_bits(0, 3)
+ text = [
+ 'Register: %d' % reg_value,
+ 'Reg: %d' % reg_value,
+ '[%d]' % reg_value,
+ ]
+ self.putg(reg_ss, reg_es, ANN_REG, text)
+ if reg_value < len(regs):
+ field_descs = regs[reg_value]
+ for field_desc in field_descs:
+ field = self.decode_field(*field_desc)
+ else:
+ text = [
+ 'Frame error: Bit count: want 32, got %d' % len(self.bits),
+ 'Frame error: Bit count',
+ 'Frame error',
+ ]
+ self.putg(ss, es, ANN_WARN, text)
+ self.bits.clear()
+
if ptype == 'BITS':
_, mosi_bits, miso_bits = data
- self.bits = mosi_bits + self.bits
+ # Cope with the lower layer SPI decoder's output convention:
+ # Regardless of wire transfer's frame format, .decode() input
+ # provides BITS in the LE order. Accumulate in MSB order here,
+ # and reverse before data processing when 'TRANSFER' is seen.
+ mosi_bits = mosi_bits.copy()
+ mosi_bits.reverse()
+ self.bits.extend(mosi_bits)